EPM7128STC100-10 vs EPM7128STC100-15N 比較
詳細並排比較 EPM7128STC100-10 由 Altera 與 EPM7128STC100-15N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7128STC100-10 - 128-Macro MAX 7000S CPLD, 10ns TQFP-100 | Intel / Altera
EPM7128STC100-10 ObsoleteIntel
EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
EPM7128STC100-15N Obsolete規格比較
| 參數 | EPM7128STC100-10 | EPM7128STC100-15N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| User I/Os | 84 | — |
| Logic Array Blocks | 8 (16 macrocells per LAB) | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family | CMOS | — |
| Supply Voltage (VCCINT) | 5 V | — |
| MultiVolt I/O Voltage | 3.3 V / 5 V | — |
| 封裝 | TQFP-100 (C100) | 100-pin TQFP |
| 腳位數 | 100 | — |
| 安裝類型 | Surface Mount | — |
| Programmability | In-System Programmable (JTAG, IEEE 1149.1), EEPROM | — |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status not in provided data] | Non-RoHS (legacy SnPb finish typical) |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 8 (16 macro cells each) |
| Maximum User I/O | — | 84 |
| Pin-to-Pin Logic Delay (tPD) | — | 15 ns (-15 speed grade) |
| Maximum Internal Frequency | — | 76.9 MHz |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Supply Voltage (VCCIO) | — | 3.3 V or 5 V (per bank) |
| Technology | — | CMOS EEPROM, in-system programmable |
| JTAG (IEEE 1149.1) | — | Yes - in-system programming |
| Output Options | — | Totem-pole or open-drain (per pin) |
| Dedicated Inputs | — | 4 global inputs |
| 生命週期狀態 | — | Obsolete (PDN effective 2017-06-01) |