EPM9320ALC84-10 vs EPM9320ARC208-10 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9320ALC84-10 disebabkan oleh Intel dan EPM9320ARC208-10 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera
EPM9320ARC208-10 ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EPM9320ALC84-10 | EPM9320ARC208-10 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Masa Terakhir Dibeli |
| Family | MAX 9000 | — |
| Device | EPM9320 | — |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 52 | — |
| Dedicated Inputs | 16 | — |
| Speed Grade | -10 (10 ns pin-to-pin delay) | — |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns |
| Supply Voltage (VCCINT) | 5.0 V | — |
| In-System Programmability | 5.0 V ISP via IEEE 1149.1 JTAG | — |
| Technology | CMOS EEPROM-based, third-generation MAX | — |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 (speed grade -10) | — |
| Kemasan | 84-pin PLCC (J-Lead) | RQFP-208 (Power Quad Flat Pack) |
| Suhu Operasi | [DATA_NEEDED: commercial/industrial grade] | [DATA_NEEDED: operating temperature range] |
| Jenis Pemasangan | Surface Mount / Through-Hole (PLCC socket) | Surface Mount |
| Status RoHS | [DATA_NEEDED] | [DATA_NEEDED: RoHS compliance status] |
| Non-Volatile Configuration | Yes (EEPROM cell, powers up in known state) | — |
| Architecture | MAX (Multiple Array MatriX) with FastTrack Interconnect | — |
| Device Family | — | MAX 9000 |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 6,000 |
| Maximum Frequency | — | 144.9 MHz |
| Tegangan Pemberi Arus | — | 5.0 V |
| Logic Blocks (LABs) | — | 16 |
| Programmability | — | EEPROM, in-system programmable via JTAG |
| JTAG Support | — | IEEE Std. 1149.1 compliant |
| Speed/Power Optimization | — | Per-macrocell programmable, 50% power mode available |