EPM9320BC356-15 vs EPM9320ALI84-10N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9320BC356-15 disebabkan oleh Altera dan EPM9320ALI84-10N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM9320BC356-15 | EPM9320ALI84-10N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX) - third generation | MAX (Multiple Array MatriX), 3rd generation |
| Macrocells | 320 | 320 |
| Pin-to-Pin Delay (max) | 15 ns | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V typical) | — |
| In-System Programmability | Yes (5.0-V ISP via JTAG) | Yes (IEEE Std. 1149.1 JTAG) |
| JTAG Interface | IEEE Std. 1149.1 compliant | — |
| Kemasan | 356-ball LBGA (BGA-356, 35x35 mm) | 84-pin PLCC (J-lead, 1.270 mm pitch) |
| Jenis Pemasangan | Surface Mount | Surface Mount (PLCC socket compatible) |
| Programmable Type | In System Programmable | — |
| Operating Temperature Grade | Commercial | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Usable Gates | — | 6,000 to 12,000 |
| Logic Array Blocks (LABs) | — | 20 |
| User I/O Pins | — | 56 |
| Pin-to-Pin Delay | — | 10 ns |
| Maximum Counter Frequency | — | 144.9 MHz |
| VCCINT (Core Supply) | — | 5.0 V |
| VCCIO (I/O Supply) | — | 3.3 V or 5.0 V |
| Input Logic Levels | — | TTL-compatible (at 5.0 V VCCINT) |
| Suhu Operasi | — | -40C to +85C (industrial) |
| Configuration Memory | — | EEPROM, non-volatile |