EPM9560ARI240-10 vs EPM9560RC-15 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9560ARI240-10 disebabkan oleh Altera dan EPM9560RC-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EPM9560RC-15 EPM9560RC-15 - 560-Macrocell MAX 9000 CPLD, 15ns, 240-RQFP | Altera / Intel

EPM9560RC-15 - 560-Macrocell MAX 9000 CPLD, 15ns, 240-RQFP | Altera / Intel

EPM9560RC-15 ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EPM9560ARI240-10 EPM9560RC-15
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Masa Terakhir Dibeli
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 12,000 12,000
Macro Cells 560 —
User I/O Pins 191 —
Kemasan 240-pin RQFP (PowerQuad Flat Pack) 240-pin RQFP (32x32 mm)
Pin-to-Pin Propagation Delay 10 ns —
Internal Frequency 144.9 MHz —
Tegangan Pemberi Arus 5.0 V —
Technology CMOS, EEPROM-based configuration —
Gambaran Suhu Operasi -40 C to +85 C (industrial) —
Jenis Pemasangan Surface Mount Surface Mount
Configuration Memory EEPROM (non-volatile, instant-on) —
Logic Architecture Multiple Array MatriX (MAX) with global interconnect array —
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Moisture Sensitivity Level [DATA_NEEDED: MSL level] —
Number of Terminals 240 —
Terminal Form Gull Wing —
Macrocells — 560
Logic Array Blocks (LABs) — 16 (40 macrocells each)
Maximum User I/O Pins — 191
Pin-to-Pin Delay (tPD1) — 15 ns
Supply Voltage (VCCINT) — 4.75 V to 5.25 V (5.0 V nominal)
Suhu Operasi — 0 C to +70 C (commercial)
Programming Interface — IEEE Std. 1149.1 JTAG (ISP)
Process Technology — CMOS EEPROM
Architecture — Multiple Array MatriX (MAX) - third generation
In-System Programmability — Yes (5.0 V ISP via JTAG)

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