EPM9560ARI240-10 vs EPM9560RC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560ARI240-10 sa pamamagitan ng Altera at EPM9560RC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM9560RC-15 - 560-Macrocell MAX 9000 CPLD, 15ns, 240-RQFP | Altera / Intel
EPM9560RC-15 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM9560ARI240-10 | EPM9560RC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 | 12,000 |
| Macro Cells | 560 | — |
| User I/O Pins | 191 | — |
| Packhaging | 240-pin RQFP (PowerQuad Flat Pack) | 240-pin RQFP (32x32 mm) |
| Pin-to-Pin Propagation Delay | 10 ns | — |
| Internal Frequency | 144.9 MHz | — |
| Volte ng Pagbibigay | 5.0 V | — |
| Technology | CMOS, EEPROM-based configuration | — |
| Hanay ng Temperature na Operasyon | -40 C to +85 C (industrial) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile, instant-on) | — |
| Logic Architecture | Multiple Array MatriX (MAX) with global interconnect array | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL level] | — |
| Number of Terminals | 240 | — |
| Terminal Form | Gull Wing | — |
| Macrocells | — | 560 |
| Logic Array Blocks (LABs) | — | 16 (40 macrocells each) |
| Maximum User I/O Pins | — | 191 |
| Pin-to-Pin Delay (tPD1) | — | 15 ns |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| Temperature na Operasyon | — | 0 C to +70 C (commercial) |
| Programming Interface | — | IEEE Std. 1149.1 JTAG (ISP) |
| Process Technology | — | CMOS EEPROM |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |
| In-System Programmability | — | Yes (5.0 V ISP via JTAG) |