EPM9560RC208-10N vs EPM9560RC208-15 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9560RC208-10N disebabkan oleh Intel dan EPM9560RC208-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Intel
EPM9560RC208-10N EPM9560RC208-10N - MAX 9000 CPLD 560 Macro 10ns 208-RQFP | Intel

EPM9560RC208-10N - MAX 9000 CPLD 560 Macro 10ns 208-RQFP | Intel

EPM9560RC208-10N ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EPM9560RC208-10N EPM9560RC208-15
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Masa Terakhir Dibeli Obsolete
Family MAX 9000 MAX 9000
Device EPM9560 —
Macro Cells 560 560 macro cells
Usable Gates 12,000 12,000 gates
Logic Array Blocks (LABs) 16 —
User I/O Pins 153 —
Pin-to-Pin Delay (tPD1) 10 ns —
Supply Voltage (VCCINT) 5.0 V —
I/O Bank Voltage (VCCIO) 5.0 V —
Kemasan 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (Power Quad Flat Pack)
Jenis Pemasangan Surface Mount Surface Mount
Process Technology CMOS EEPROM —
Programmability In-system via IEEE 1149.1 JTAG —
Suhu Operasi [DATA_NEEDED: operating temperature grade] [DATA_NEEDED: operating temperature range]
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Device Type — EEPROM-based Complex Programmable Logic Device (CPLD)
Pin-to-Pin Delay — 15 ns
Counter Speed — 117.6 MHz
Tegangan Pemberi Arus — 5.0 V
Configuration Technology — EEPROM (non-volatile)
In-System Programmability — Yes, via IEEE Std. 1149.1 JTAG
Number of I/O Pins — [DATA_NEEDED: number of I/O pins]
Logic Array Blocks — [DATA_NEEDED: number of logic array blocks]
Speed Grade — -15 (15 ns pin-to-pin)
Architecture — Third-generation Multiple Array MatriX (MAX)

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