EPM9560RC208-15 vs EPM9560RC208-15C Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9560RC208-15 disebabkan oleh Altera dan EPM9560RC208-15C disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM9560RC208-15 EPM9560RC208-15C
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 9000 MAX 9000
Device Type EEPROM-based Complex Programmable Logic Device (CPLD) EEPROM-based CPLD (EPLD)
Usable Gates 12,000 gates 12,000
Macro Cells 560 macro cells —
Pin-to-Pin Delay 15 ns —
Counter Speed 117.6 MHz —
Tegangan Pemberi Arus 5.0 V —
Configuration Technology EEPROM (non-volatile) —
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG Yes, via IEEE Std. 1149.1 JTAG
Kemasan 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP
Jenis Pemasangan Surface Mount Surface Mount
Suhu Operasi [DATA_NEEDED: operating temperature range] —
Number of I/O Pins [DATA_NEEDED: number of I/O pins] —
Logic Array Blocks [DATA_NEEDED: number of logic array blocks] —
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Speed Grade -15 (15 ns pin-to-pin) -15 (15 ns)
Architecture Third-generation Multiple Array MatriX (MAX) —
Macrocells — 560
User I/O Pins — 149
Propagation Delay (tPD) — 15 ns
Maximum Counter Frequency — 117.6 MHz
Supply Voltage Range — 4.75 V to 5.25 V
Nominal Supply Voltage — 5.0 V
I/O Voltage Compatibility — 3.3 V or 5 V
Configuration Memory — EEPROM (non-volatile)
Gambaran Suhu Operasi — 0C to +70C (commercial)
Logic Architecture — Multiple Array MatriX (MAX) third generation

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