10AX115H3F34I2SG - Arria 10 GX FPGA 1.15M LE | Intel
MPN: 10AX115H3F34I2SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4250 | $4,250.00 |
| 10 | $4085 | $40,850.00 |
| 25 | $3960 | $99,000.00 |
| 50 | $3820 | $191,000.00 |
| 100 | $3675 | $367,500.00 |
Drop-in alternatives for 10AX115H3F34I2SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AX115H3F34I2LG
✅ Drop-In✓ In Stock
$6800 / Unit
View Datasheet →10AX115H3F34E2LG
✅ Drop-In✓ In Stock
$6550 / Unit
View Datasheet →10AX115H2F34I2SG
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$3640 / Unit
View Datasheet →10AX115H2F34I2LG
✅ Drop-In✓ In Stock
$4995 / Unit
View Datasheet →10AX115H1F34I1SG
✅ Drop-In✓ In Stock
$6500 / Unit
View Datasheet →10AX090U3F45I2SG
✅ Drop-In✓ In Stock
$7450 / Unit
View Datasheet →10AX115H3F34I2SG Maximum Ratings & Electrical Characteristics
| Series | Arria 10 GX |
| Family | 10AX115 |
| Logic Elements | 1,150,000 |
| Embedded Memory | 68,857,856 bits (~8.4 MByte) |
| Number of I/O | 504 |
| Core Voltage | 0.87 V to 0.93 V |
| Package | 1152-BBGA, FCBGA |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to 100C (TJ) |
| Grade | Industrial |
| Process Technology | 20 nm Tri-Gate |
| Supplier Device Package | 1152-FCBGA |
| Configuration Method | SRAM-based, volatile |
| Transceivers | Yes (GX variant, up to 14.1 Gbps) |
10AX115H3F34I2SG 1152-fcbga Pin Configuration Guide
Complete pinout information for 10AX115H3F34I2SG (1152-fcbga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX115H3F34I2SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115H3F34I2SG is suitable for 7 applications: High-Speed Telecom Backhaul, Broadcast Video Processing, ASIC Prototyping, Software Defined Radio (SDR), Medical Imaging Acceleration, Industrial Machine Vision, Test and Measurement Instrumentation.
High-Speed Telecom Backhaul
The 10AX115H3F34I2SG's 1.15M logic elements and Arria 10 GX transceivers up to 14.1 Gbps make it ideal for telecom backhaul line cards. Placed on a CFP/CFP2 pluggable backplane, the FPGA performs packet classification, traffic shaping, and OTN/SONET framer logic with deterministic latency. The 504 user I/O support 10G Ethernet, CPRI, and OBSAI interfaces simultaneously. Hard IP cores for 10G Ethernet MAC and PCI Express Gen3 offload common protocol functions, freeing soft logic for customer-differentiated features. The 20 nm process and hardened DSP blocks keep typical backhaul designs under 30 W.
Recommended
Broadcast Video Processing
The 10AX115H3F34I2SG drives 4K/UHD video processing pipelines with sufficient logic capacity for color-space conversion, scaling, deinterlacing, and HDR metadata insertion. The 504 user I/O aggregate SDI, HDMI, and DisplayPort streams at up to 12G-SDI rates. Hardened memory controllers feed multiple DDR3/DDR4 banks with low latency. The GX transceivers accept uncompressed video over 10G Ethernet links for contribution feeds. Industrial temperature grade suits 24/7 broadcast rack environments. The same device can simultaneously implement video processing and overlay graphics.
Recommended
ASIC Prototyping
The 10AX115H3F34I2SG provides 1.15M logic elements for prototyping mid-complexity ASICs before tape-out, enabling software bring-up and verification on real hardware months before silicon return. The 504 I/O map to FMC connectors and high-speed Mezzanine cards for full ASIC peripheral emulation. Hardened DDR3/DDR4 controllers replicate production memory timing. Quartus Prime supports incremental synthesis to accelerate design iterations. Multiple FPGAs can be chained via the transceivers to partition large ASIC designs.
Recommended
Software Defined Radio (SDR)
The 10AX115H3F34I2SG's hardened DSP blocks and up to 14.1 Gbps transceivers enable wideband SDR platforms covering LTE, 5G NR sub-6 GHz, and tactical radio waveforms. The 504 I/O connect to RF ADC/DAC daughtercards via JESD204B/C links. Floating-point hardened operators accelerate channel estimation, FFT, and turbo decoding in soft logic. Industrial temperature grade suits outdoor base station and tactical radio enclosures. Partial reconfiguration enables runtime swapping of waveform personalities without rebooting.
Recommended
Medical Imaging Acceleration
The 10AX115H3F34I2SG accelerates CT, MRI, and ultrasound image reconstruction pipelines with its 1.15M logic elements and DSP blocks. The 504 user I/O accept raw sensor data at multi-Gbps rates via LVDS and sub-LVDS, while transceivers aggregate 10G Ethernet for distribution to PACS archives. Hardened floating-point operators speed up back-projection, iterative reconstruction, and beamforming. Industrial temperature and reliability qualifications support medical device regulatory submissions. Long-term availability through Intel's embedded roadmap supports multi-year product lifecycles.
Recommended
Industrial Machine Vision
The 10AX115H3F34I2SG drives multi-camera machine vision inspection lines with sub-millisecond latency. The 504 I/O interface to Camera Link, CoaXPress, and GigE Vision cameras via hard IP cores. Logic capacity supports simultaneous defect detection, OCR, and 3D point-cloud processing per camera stream. Transceivers aggregate multiple 10G links to central servers for archival and AI inference. Industrial temperature and ECC-protected memory make the device suitable for 24/7 factory floor operation.
Recommended
Test and Measurement Instrumentation
The 10AX115H3F34I2SG's 14.1 Gbps transceivers and 504 user I/O enable high-end oscilloscope, protocol analyzer, and arbitrary waveform generator designs. Logic capacity implements deep acquisition memory, trigger logic, and DSP post-processing simultaneously. Hard IP cores handle PCI Express Gen3 host connectivity for streaming captured data to analysis PCs. The 20 nm process keeps per-channel power low for dense channel-count modules. Industrial temperature and long-term availability suit ATE platform roadmaps.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115H3F34I2SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115H3F34I2LG | 10AX115H3F34E2LG | 10AX115H2F34I2SG | 10AX115H1F34I1SG | 10AX090U3F45I2SG |
|---|---|---|---|---|---|---|
| Package | 1152-FCBGA | 1152-FCBGA - same | 1152-FCBGA - same | 1152-FCBGA - same | 1152-FCBGA - same | 1152-FCBGA - same |
| Brand | Intel | Intel - same | Intel - same | Intel - same | Intel - same | Intel - same |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 900,000 |
| Speed Grade | -3 (fastest) | -3 | -2 | -2 | -1 (slowest) | -3 |
| Temperature Grade | Industrial (-40C to 100C) | Industrial | Extended | Industrial | Industrial | Industrial |
| Number of I/O | 504 | 504 | 504 | 504 | 504 | 504 |
| Packing Media | Tray | Tape-and-Reel | Tape-and-Reel | Tray | Tray | Tray |
| Family Variant | 10AX115 | 10AX115 | 10AX115 | 10AX115 | 10AX115 | 10AX090 |
Key Differentiators
- Highest speed grade in the 10AX115 family (vs 10AX115H2F34I2SG)
- Same package as the entire 10AX115 family (vs 10AX115H3F34I2LG)
- Highest logic density in the Arria 10 family (vs 10AX090U3F45I2SG)
Design Notes
The 10AX115H3F34I2SG in FCBGA-1152 can dissipate 25-40 W at full transceiver and logic utilization. Attach a high-performance heatsink with thermal interface material rated for industrial temperature. Use thermal vias under the exposed pad of the FCBGA and at least 4-layer PCB with continuous ground planes to spread heat. Estimate: at 35 W and theta_JA of 8 C/W (with heatsink), junction rises 280 C above 25 C ambient, exceeding the 100 C TJ limit - ensure adequate airflow or cold-plate cooling for sustained full-load operation.
The FCBGA-1152 substrate demands high-density PCB layout: microvias (0.1 mm or smaller), fine line/space (4 mil or below), and stack-up of 8+ layers for transceiver signal integrity. Decouple every transceiver and I/O bank with 0.1 uF and 10 uF capacitors placed within 5 mm of the power pins. Keep high-speed serial traces 100 ohm differential, length-matched within 5 mil for lanes of the same group, and reference continuous ground planes on adjacent layers.
Do not substitute the H3 (speed grade -3) with H2 or H1 speed grades in designs that close timing on the highest transceiver or logic frequency. Verify the Quartus Prime fitter report shows positive slack on all critical paths before committing to a lower speed grade. Also ensure boot flash capacity exceeds the compressed bitstream size; Arria 10 GX designs with hard IP often exceed 100 Mbits uncompressed.
Arria 10 GX transceivers at 14.1 Gbps require pre-emphasis and equalization settings tuned per channel via the Quartus Prime Transceiver Toolkit. Lossy backplane channels (>10 inch FR4) need CTLE and DFE enabled. AC-coupling capacitors must be 100 nF X7R placed within 200 mil of the FPGA transmitter pins. Reference clock jitter must be below 200 fs RMS for 10G Ethernet compliance.
Compliance Information
RoHS compliant per Intel environmental disclosures for Arria 10 family. Not AEC-Q100 qualified - this device is for industrial/commercial use. AEC-Q100 qualification must be specified separately if required.
