10AX115H2F34I2LG - Arria 10 GX FPGA, 1.15M Logic Elements | Intel
MPN: 10AX115H2F34I2LG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5985 | $5,985.00 |
| 10 | $5750 | $57,500.00 |
| 100 | $5490 | $549,000.00 |
| 500 | $5250 | $2,625,000.00 |
| 1,000 | $4995 | $4,995,000.00 |
10AX115H2F34I2LG Overview
A Field-Programmable Gate Array (FPGA) is a reconfigurable integrated circuit whose logic fabric, routing, and I/O can be programmed after manufacturing to implement arbitrary digital functions. The Arria 10 family sits between Cyclone (low-power/low-cost) and Stratix (highest-performance) in Intel's FPGA portfolio, targeting mid- to high-end applications that need transceiver bandwidth and DSP throughput without the absolute top-end cost of Stratix 10. Within the broader taxonomy, the 10AX115H2F34I2LG is part of the Arria 10 GX sub-family (transceivers enabled), distinct from Arria 10 GT (higher transceiver rate) and Arria 10 SX (HPS + FPGA SoC integration).
Key features include 504 maximum user I/O pins, a 1.5 GHz core fabric, support for DDR4/QDR-IV external memory interfaces, and an industrial temperature grade (-40C to +100C ambient). The device also integrates 24 backplane-capable transceivers up to 14.4 Gbps, hardware PCI Express Gen3 hard IP blocks, and partial reconfiguration support for in-field updates. With 1152 package balls and a flip-chip BGA construction, the package provides high I/O density and excellent electrical performance for high-speed serial links.
The 10AX115H2F34I2LG's combination of logic capacity, transceiver count, and hard IP makes it well suited to applications such as 4K video processing, software-defined radio (SDR), radar signal processing, and high-speed serial protocol bridges (PCIe Gen3, 10GbE, 40GbE, JESD204B/C, CPRI). Compared with smaller Arria 10 variants like the 10AS066H2F34I2SG, the 10AX115H2F34I2LG offers nearly 1.7x the logic elements and roughly 1.5x the embedded memory for designs that need additional fabric headroom.
Typical applications include broadcast studio video processing, medical imaging front-ends, defense signal intelligence, and high-end test & measurement. When migrating designs from earlier Arria V or Stratix V devices, Quartus Prime provides device-aware migration scripts that re-target pin assignments to the 10AX115H2F34I2LG footprint.
Designers should carefully review the device's power estimation early in the design cycle using Intel's Early Power Estimator (EPE) tool, since a fully loaded 1.15M-LE design with multiple 14.4 Gbps transceivers can exceed 30 W. Proper PCB stack-up, decoupling strategy, and thermal management are mandatory. Quartus Prime Pro Edition supports the 10AX115H2F34I2LG with full synthesis, place-and-route, and timing analysis.
This page synthesizes distributor pricing, parametric alternatives, and practical design considerations drawn from the Intel Arria 10 datasheet and major distributor listings (as of 2026-09-05), not found in any single source.
Drop-in alternatives for 10AX115H2F34I2LG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with 10AX115H2F34I2LG (same form factor and footprint) — differing in Package, DSP Blocks, Speed Grade, Transceivers, Embedded Memory.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AX115H2F34I1SG
✅ Drop-In✓ In Stock
$3700 / Unit
View Datasheet →10AX115H2F34E2SG
✅ Drop-In✓ In Stock
$5500 / Unit
View Datasheet →10AX115H2F34E2LG
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$5950 / Unit
View Datasheet →10AX115H2F34E1SG
✅ Drop-In✓ In Stock
$3300 / Unit
View Datasheet →10AX115H1F34I1SG
✅ Drop-In✓ In Stock
$6500 / Unit
View Datasheet →10AX115H1F34E1SG
✅ Drop-In✓ In Stock
$2895 / Unit
View Datasheet →10AX090U4F45I3LG
✅ Drop-In✓ In Stock
$7450 / Unit
View Datasheet →10AX115H2F34I2LG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements (LE) | 1,150,000 |
| Embedded Memory Bits | 68,857,560 |
| Maximum User I/O | 504 |
| Transceivers | 24 channels, up to 14.4 Gbps |
| Package | 1152-ball FCBGA (BBGA) |
| Process Technology | 20 nm TSMC |
| Core Voltage | 0.9 V (nominal) |
| Temperature Grade | Industrial (-40C to +100C) |
| Speed Grade | -2 |
| DSP Blocks | Hard floating-point DSP |
| Memory Controller | Hardened external memory interface (DDR4/QDR-IV) |
| PCIe Hard IP | PCI Express Gen3 x8 |
| Configuration | FPGA (SRAM-based, volatile) |
| RoHS Status | Compliant (per distributor listing) |
| Mounting Type | Surface Mount (BGA) |
10AX115H2F34I2LG 1152-ball fcbga (bbga) Pin Configuration Guide
Pin configuration for 10AX115H2F34I2LG (1152-ball fcbga (bbga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX115H2F34I2LG.
Refer to the datasheet for full pin configuration.
Typical Applications
10AX115H2F34I2LG is suitable for 7 applications: 4K Video Processing Pipeline, Software Defined Radio (SDR), Radar Signal Processing, High-Speed Protocol Bridge, Medical Imaging Front-End, Broadcast Studio Video Switcher, Test & Measurement Instrumentation.
4K Video Processing Pipeline
The 10AX115H2F34I2LG is well matched to 4K video processing because its 1,150,000 logic elements can sustain multi-channel video pipelines at 60 fps with HDR processing and color-space conversion. The hard floating-point DSP blocks accelerate deinterlacing and scaling kernels, while the 24 transceivers up to 14.4 Gbps enable uncompressed multi-stream SDI, HDMI 2.0, and DisplayPort 1.4 I/O without external bridge chips. Place-and-route headroom is preserved even at full fabric utilization. Compared with the smaller 10AS066H2F34I2SG, the AX115 variant avoids fabric overflow when implementing 4:4:4 chroma sub-sampling with 10-bit precision.
Recommended
Software Defined Radio (SDR)
The 10AX115H2F34I2LG's 24 transceivers up to 14.4 Gbps and 1.15M logic elements make it a strong fit for wideband SDR platforms that must simultaneously digitize and demodulate multiple RF channels. The hardened memory controller supports DDR4 sample buffers at multi-gigasample rates, and the hard floating-point DSP blocks accelerate FFT/iFFT and channelization kernels with predictable timing closure. Industrial temperature grade permits deployment in outdoor base-station enclosures. Quartus Prime DSP Builder provides model-based design flows for rapid waveform development.
Recommended
Radar Signal Processing
The 10AX115H2F34I2LG delivers the logic density and DSP throughput required for phased-array radar signal processing, where each antenna channel requires dedicated beamforming, FFT, and target-detection hardware. With 1.15M logic elements, designers can implement 32+ parallel channel pipelines with 4096-point FFTs at real-time sample rates exceeding 500 MSPS. The hardened memory controller sustains high-bandwidth data movement to DDR4 buffers, while 24 transceivers aggregate digitized ADC data from across the array. Industrial temperature grade supports ground-based and shipboard radar platforms.
Recommended
High-Speed Protocol Bridge
The 10AX115H2F34I2LG is well suited to multi-protocol bridging applications (PCIe Gen3 to 40GbE, JESD204B to Ethernet, CPRI to 10GbE) because of its 24 transceivers at 14.4 Gbps and hard PCIe Gen3 IP block. Designers can implement protocol aggregation, packet processing, and flow management without external bridge ASICs, reducing BOM cost and latency. The industrial temperature grade permits deployment in telco edge equipment and industrial networking gear. Quartus Prime provides pre-verified IP cores for PCIe, 10GbE MAC/PCS, and JESD204B/C, accelerating time-to-market.
Recommended
Medical Imaging Front-End
The 10AX115H2F34I2LG supports CT, MRI, and ultrasound imaging front-ends where parallel channel processing of digitized sensor data is required. Its 1.15M logic elements enable 64-channel ultrasound beamformers and real-time image reconstruction, while the hardened memory controller moves raw channel data to DDR4 buffers at multi-GB/s rates. The 24 transceivers aggregate data from multiple ADC front-ends and link to the host processor over PCIe Gen3. Industrial temperature grade supports deployment in clinical imaging carts and operating-room equipment.
Recommended
Broadcast Studio Video Switcher
The 10AX115H2F34I2LG's 1.15M logic elements and 24 transceivers at 14.4 Gbps make it suitable for broadcast studio video switchers and routers that must aggregate 12G-SDI, HDMI 2.0, and DisplayPort 1.4 streams with frame-accurate switching. Hard DSP blocks accelerate up/down/cross-conversion and HDR-to-SDR mapping, while the hardened memory controller supports multi-channel frame buffers. Industrial temperature grade supports 24/7 studio operation. Quartus Prime provides broadcast reference designs that pass SMPTE ST 2059 and ST 2022 compliance tests.
Recommended
Test & Measurement Instrumentation
The 10AX115H2F34I2LG integrates the logic, DSP, and high-speed serial I/O required to implement high-end oscilloscopes, protocol analyzers, and bit-error-rate testers. Its 1.15M logic elements support real-time triggering and pattern generation across multiple channels, while the 24 transceivers at 14.4 Gbps aggregate digitized signal data from ADC front-ends. The hardened memory controller sustains deep capture buffers in DDR4 memory. Industrial temperature grade supports bench-top and portable instrument form factors. Quartus Prime DSP Builder enables model-based firmware development for signal-analysis kernels.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115H2F34I2LG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115H2F34I1SG | 10AX115H2F34E2SG | 10AX115H2F34E2LG | 10AX115H2F34E1SG | 10AX115H1F34I1SG | 10AX115H1F34E1SG | 10AX090U4F45I3LG |
|---|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-ball FCBGA (F34) | 1152-ball FCBGA (F34) - same | 1152-ball FCBGA (F34) - same | 1152-ball FCBGA (F34) - same | 1152-ball FCBGA (F34) - same | 1152-ball FCBGA (F34) - same | 1152-ball FCBGA (F34) - same | 1152-ball FCBGA (F45) - different ballout |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 (H1 variant) | 1,150,000 (H1 variant) | 900,000 (-22%) |
| Embedded Memory (Mbits) | 65.7 Mbits (68,857,560 bits) | 65.7 Mbits | 65.7 Mbits | 65.7 Mbits | 65.7 Mbits | 65.7 Mbits | 65.7 Mbits | 52.4 Mbits |
| Maximum User I/O | 504 | 504 | 504 | 504 | 504 | 504 | 504 | 448 |
| Transceivers (max) | 24 @ 14.4 Gbps | 24 @ 14.4 Gbps | 24 @ 14.4 Gbps | 24 @ 14.4 Gbps | 24 @ 14.4 Gbps | 24 @ 14.4 Gbps | 24 @ 14.4 Gbps | 36 @ 14.4 Gbps (more channels) |
| Speed Grade | -2 | -1 | -2 | -2 | -1 | -1 | -1 | -3 |
| Temperature Grade | Industrial (-40C to +100C) | Industrial | Extended | Extended | Extended | Industrial | Extended | Industrial |
| Process / Core Voltage | 20 nm / 0.9 V | 20 nm / 0.9 V | 20 nm / 0.9 V | 20 nm / 0.9 V | 20 nm / 0.9 V | 20 nm / 0.9 V | 20 nm / 0.9 V | 20 nm / 0.9 V |
Key Differentiators
- Highest density in the F34-footprint Arria 10 AX sub-family (vs 10AS066H2F34I2SG)
- Industrial temperature grade with same die as extended temp variants (vs 10AX115H2F34E2LG)
- 24 transceivers at 14.4 Gbps for high-throughput serial I/O (vs 10AX090U4F45I3LG)
Design Notes
Estimated: A fully loaded 10AX115H2F34I2LG design at 100% logic utilization with 24 active 14.4 Gbps transceivers can draw 30-40 W. Use Intel's Early Power Estimator (EPE) spreadsheet early in the design cycle to predict power dissipation and thermal envelope. The 1152-ball FCBGA requires a high-performance PCB stack-up with adequate copper pour and thermal vias to maintain junction temperature within the 100C industrial limit. Without proper thermal design, the device will throttle and may trigger thermal shutdown during long inference or signal-processing runs.
The 1152-ball FCBGA package requires a high-density PCB with microvia stack-ups (typically 6-12 layers, 0.4 mm pitch escape). Route all 24 transceiver channels with matched differential pair lengths (within 0.05 mm), maintain 100 ohm differential impedance, and place DC-blocking capacitors and common-mode chokes close to the FPGA balls. Reference Intel's Arria 10 PCB design guide (AN 707) for the recommended stack-up and via pattern, and verify signal integrity with 3D EM simulation before tape-out.
Do not confuse 'AX' (high-density, transceiver-enabled) with 'AS' (standard, no transceivers) sub-families when migrating designs between Arria 10 variants. The 10AS066H2F34I2SG shares the same F34 footprint but lacks the transceiver hard IP, so designs that use more than 660K LE or any transceiver channels will fail compilation on the AS sub-family. Also verify speed-grade compatibility: -2 is the fastest, -3 is the slowest - downgrading can break timing closure.
Compliance Information
RoHS and lead-free status per Intel product page; halogen-free status not explicitly listed in distributor data. AEC-Q100 not applicable - this is a high-end FPGA, not an automotive-qualified IC.
