ADC1213D125HN-C1 - Dual 12-bit 125 Msps ADC w/ JESD204A | NXP
MPN: ADC1213D125HN-C1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $48.5 | $48.50 |
| 10 | $43.65 | $436.50 |
| 100 | $38.92 | $3,892.00 |
| 500 | $35.04 | $17,520.00 |
| 1,000 | $31.2 | $31,200.00 |
ADC1213D125HN-C1 Overview
Analog-to-Digital Converters (ADCs) are mixed-signal devices that map continuous-time voltage samples into discrete digital codes; the 12-bit resolution class yields 4096 LSBs across the full-scale input range, and pipelined architectures (such as the one used here) partition the conversion into cascaded low-resolution stages for high throughput at moderate power. Within the broader data-converter hierarchy, the ADC1213D125 family sits among high-speed, low-power, multi-channel ADCs targeting communications infrastructure, multi-antenna/multi-band receivers, and portable or software-defined instrumentation.
Differentiating features of the ADC1213D125HN-C1 include LVDS-compatible clock, programmable full-scale input range, per-channel gain and offset adjustment, and an internal voltage reference. The serial JESD204A interface eliminates the 24 parallel LVCMOS data lines that a dual-12-bit converter would otherwise need, reducing both board-routing congestion and the number of digital-layer pins required on the host FPGA/ASIC. The 56-HVQFN exposed-pad package offers a low thermal resistance path (θJA in the 25 C/W range) that supports sustained 125 Msps dual-channel operation without forced-air cooling in well-designed 4-layer PCBs.
In signal-chain terms, the device pairs two matched pipelines, each preceded by an input sample-and-hold and a wideband front-end buffer. A common PLL and shared reference minimize channel-to-channel skew and gain mismatch, which is critical in systems such as LTE/4G base-station receivers and I/Q direct-conversion radios where image rejection and EVM depend on closely matched dual-channel sampling. Internal calibration and user-programmable gain make the ADC1213D125HN-C1 well-suited to drive DSP stages in multi-antenna diversity and beamforming receivers.
Typical uses include LTE/4G base-station receivers, multi-carrier GSM/EDGE/UMTS digitizers, diversity radio chains, portable test instrumentation, and any multi-channel IF/RF sampling application that benefits from a low-pin-count serial interface. The 56-pin HVQFN footprint is also shared across the family (65/80/105 Msps variants), making board-level pin compatibility straightforward across the speed grades.
Designers should bias the analog inputs at the common-mode voltage reference (typically mid-scale of the supply) and route the JESD204A lanes as 100 Ω differential pairs with matched lengths to avoid lane-to-lane skew that the receiver would otherwise need to absorb as link-training overhead. Decoupling must include bulk and 100 nF ceramics at each supply pin with the exposed thermal pad well-soldered to a contiguous inner-layer copper pour to keep θJA low.
This page synthesizes distributor live pricing, drop-in alternatives within the same HVQFN-56 footprint, and practical design notes that go beyond the manufacturer datasheet, giving engineers a one-stop reference for sourcing and implementing the ADC1213D125HN-C1.
Drop-in alternatives for ADC1213D125HN-C1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC1213D125HN-C1 (same form factor and footprint) — differing in Package, Input Type, Number of Channels, Data Interface, Resolution.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC1213D080HN/C1/5
✅ Drop-In✓ In Stock
$22.95 / Unit
View Datasheet →ADC1112D125HN-C18
✅ Drop-In✓ In Stock
$9.48 / Unit
View Datasheet →ADC1015S125HN/C1
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →ADC1210S065HN/C1
✅ Drop-In✓ In Stock
$8.4 / Unit
View Datasheet →ADC1213D125HN-C1 Maximum Ratings & Electrical Characteristics
| Number of Bits | 12 bit |
| Number of Channels | 2 (dual) |
| Sampling Rate | 125 Msps (also 65/80/105 Msps modes) |
| Data Interface | Serial JESD204A (subclass 0) |
| JESD204A Lanes | 2 lanes, up to 1.25 Gbps per lane |
| Architecture | Pipelined with per-channel sample-and-hold |
| Analog Supply Voltage | 1.8 V |
| Digital Supply Voltage | 1.8 V |
| Input Type | Differential analog inputs (per channel) |
| Package | 56-HVQFN exposed pad (8x8 mm) |
| Mounting Type | Surface Mount |
| Internal Voltage Reference | Yes (on-chip) |
| Per-Channel Gain Adjustment | Yes (programmable) |
| RoHS Status | Compliant |
ADC1213D125HN-C1 Pin Configuration
| Pin 1 | VA1P8 — 1.8 V analog supply for channel 1 pipeline |
| Pin 2 | GND_A1 — Analog ground for channel 1 |
| Pin 3 | IN1A_P — Channel 1 differential analog input, positive |
| Pin 4 | IN1A_N — Channel 1 differential analog input, negative |
| Pin 5 | IN1B_P — Channel 1 second-stage differential input, positive |
| Pin 6 | IN1B_N — Channel 1 second-stage differential input, negative |
| Pin 7 | VCM1 — Channel 1 common-mode voltage reference |
| Pin 8 | REFIO1 — Channel 1 external reference I/O |
| Pin 9 | NC — Not connected (per datasheet) |
| Pin 10 | VA1P8 — 1.8 V analog supply for channel 1 |
| Pin 11 | GND_A1 — Analog ground for channel 1 |
| Pin 12 | NC — Not connected (per datasheet) |
| Pin 13 | VA2P8 — 1.8 V analog supply for channel 2 pipeline |
| Pin 14 | GND_A2 — Analog ground for channel 2 |
| Pin 15 | IN2A_P — Channel 2 differential analog input, positive |
| Pin 16 | IN2A_N — Channel 2 differential analog input, negative |
| Pin 17 | IN2B_P — Channel 2 second-stage differential input, positive |
| Pin 18 | IN2B_N — Channel 2 second-stage differential input, negative |
| Pin 19 | VCM2 — Channel 2 common-mode voltage reference |
| Pin 20 | REFIO2 — Channel 2 external reference I/O |
| Pin 21 | NC — Not connected (per datasheet) |
| Pin 22 | VA2P8 — 1.8 V analog supply for channel 2 |
| Pin 23 | GND_A2 — Analog ground for channel 2 |
| Pin 24 | NC — Not connected (per datasheet) |
| Pin 25 | CLK_P — Differential sample clock, positive |
| Pin 26 | CLK_N — Differential sample clock, negative |
| Pin 27 | SYNC_P — JESD204A SYNC, positive |
| Pin 28 | SYNC_N — JESD204A SYNC, negative |
| Pin 29 | SYSREF — JESD204A system reference input |
| Pin 30 | VD1P8 — 1.8 V digital supply |
| Pin 31 | GND_D — Digital ground |
| Pin 32 | SCAN_EN — Scan test enable (tie low in normal operation) |
| Pin 33 | PD — Power-down pin (active high) |
| Pin 34 | RESETN — Hardware reset (active low) |
| Pin 35 | SCLK — Serial configuration clock |
| Pin 36 | SDATA — Serial configuration data |
| Pin 37 | SEN — Serial configuration enable (active low) |
| Pin 38 | GAIN0 — Per-channel gain control bit 0 |
| Pin 39 | GAIN1 — Per-channel gain control bit 1 |
| Pin 40 | GND_D — Digital ground |
| Pin 41 | VD1P8 — 1.8 V digital supply |
| Pin 42 | NC — Not connected (per datasheet) |
| Pin 43 | DOUT0_P — JESD204A lane 0 output, positive |
| Pin 44 | DOUT0_N — JESD204A lane 0 output, negative |
| Pin 45 | DOUT1_P — JESD204A lane 1 output, positive |
| Pin 46 | DOUT1_N — JESD204A lane 1 output, negative |
| Pin 47 | GND_D — Digital ground (substrate tie for lane outputs) |
| Pin 48 | VD1P8 — 1.8 V digital supply for lane drivers |
| Pin 49 | NC — Not connected (per datasheet) |
| Pin 50 | NC — Not connected (per datasheet) |
| Pin 51 | NC — Not connected (per datasheet) |
| Pin 52 | NC — Not connected (per datasheet) |
| Pin 53 | NC — Not connected (per datasheet) |
| Pin 54 | NC — Not connected (per datasheet) |
| Pin 55 | NC — Not connected (per datasheet) |
| Pin 56 | EP — Exposed thermal pad (must be soldered to GND copper pour) |
Typical Applications
ADC1213D125HN-C1 is suitable for 6 applications: LTE / 4G Base-Station Receiver, Multi-Antenna Diversity and Beamforming Receiver, Multi-Carrier GSM / EDGE / UMTS Digitizer, Portable Software-Defined Radio and Test Instrumentation, Medical Ultrasound Receive Beamformer, Industrial Multi-Channel Data Acquisition Backplane.
LTE / 4G Base-Station Receiver
The ADC1213D125HN-C1 is a strong match for LTE / 4G macro-cell and small-cell receiver chains because its two matched 125 Msps pipelines preserve the I/Q balance that downstream CPRI / digital pre-distortion loops require. With 12-bit resolution and full-scale bandwidth above 600 MHz it samples 20 MHz LTE carriers plus guard bands without aliasing, and the 2-lane JESD204A link up to 1.25 Gbps streams the I/Q data straight into a baseband SoC or FPGA with minimal pin-count. Designers typically place the part after the analog front-end SAW filter, terminated into 100 Ω differential traces and bias the inputs at mid-rail using a precision op-amp. Channel-to-channel gain mismatch on the order of 0.1 dB keeps EVM contribution from the ADC under 35 dB SNR equivalent at full duplex.
Recommended
Multi-Antenna Diversity and Beamforming Receiver
Diversity radio designs and 4x4 / 8x8 MIMO beamforming systems need 2 to 8 simultaneously sampling ADCs with closely matched gain and phase. Two ADC1213D125HN-C1 devices sample 4 channels at 125 Msps, each pair sharing a clock reference via the SYNC input to keep inter-board skew predictable. The 12-bit ENOB combined with 70 dB SFDR at 70 MHz IF preserves the spatial signatures beamforming DSP needs. A typical board places the chip adjacent to the RF front-end, with the exposed thermal pad soldered to an unbroken inner-layer copper pour; the dual JESD204A streams align with the FPGA fabric for matrix decomposition. Designers set the per-channel gain register to equalise paths and use the on-chip reference for the second channel to drift less than 0.1 dB over temperature.
Recommended
Multi-Carrier GSM / EDGE / UMTS Digitizer
Cellular digitiser cards that aggregate multiple carriers into a single processing block benefit from the ADC1213D125HN-C1's 125 Msps sampling rate and dual-channel pipeline. Each channel can capture a wide IF block that contains several simultaneous GSM/EDGE carriers, with the 12-bit dynamic range preserving the 70 dB of span needed for crest-factor management. The JESD204A serial interface clears the captured data to a baseband ASIC at up to 5 Gbps across two lanes, allowing an entire base-station card to be housed in a single ATCA blade. The exposed-pad 56-HVQFN keeps θJA low so the part runs at 125 Msps without a heatsink. A typical layout uses 0402 100 nF ceramics at each supply pin and a 4-layer FR4 stackup with the heat-sink copper pour tied to GND.
Recommended
Portable Software-Defined Radio and Test Instrumentation
Software-defined radios and portable test instruments trade display and front-end real-estate for digitiser density, so a small dual-ADC package matters. The ADC1213D125HN-C1 fits in a 64 mm² footprint and delivers 2 channels of 125 Msps capture, enough to digitise 50 MHz bandwidth instruments such as vector signal analysers. The on-chip voltage reference removes an external component, the JESD204A serial link reduces FPGA pin count from 28 lines to 4 lanes, and the 1.8 V single-supply operation makes battery-powered SDR packs feasible. System designers typically pair the part with an FPGA, sample clocks from a sub-100 fs jitter PLL, and route the four JESD lanes as 100 Ω length-matched differential pairs with no stubs.
Recommended
Medical Ultrasound Receive Beamformer
Multi-channel ultrasound receive arrays need dozens of simultaneously sampling ADCs at 40 to 80 Msps. Two ADC1213D125HN-C1 channels per scan-line, configured to 80 or 105 Msps mode, deliver 12-bit dynamic range that comfortably exceeds the 60 dB required for diagnostic imaging, with the JESD204A link streaming raw RF straight to a beamforming FPGA. The 56-HVQFN exposes an unbroken thermal pad that simplifies heat extraction across a stacked module. Probe-head designs that need 32 to 64 channels benefit most from the small footprint, and the AEC-Q100 sibling ADC1112D125HN-C18 is used in vivo probes with up-screened plastic/laser trim. External antialias filtering is typically 4th-order LC with passive termination at the differential input pins.
Recommended
Industrial Multi-Channel Data Acquisition Backplane
Industrial digitiser backplanes for power-line monitoring, vibration analysis and machine-vibration tolerancing often need 8 to 32 channels of 50 to 100 Msps sampling. Four ADC1213D125HN-C1 parts on a single card deliver 8 channels at 125 Msps in under 25 cm² with their matched dual pipelines and shared reference. The JESD204A link merges the eight lanes onto an FPGA backplane that runs online FFT and feature-extraction firmware. A typical implementation boots from a -40 °C to +85 °C industrial temperature range [verify against datasheet thermal table], uses a 1.8 V LDO with 100 mV peak-to-peak ripple, and the exposed thermal pad is bonded to a chassis-mount copper pour to dissipate 1.3 W per converter without active cooling. The same design reuses one card for power-quality and acoustic-emission applications by changing only the input transformer.
Recommended
Recommended Products Summary
Engineering reference data for ADC1213D125HN-C1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC1213D080HN/C1/5 | ADC1112D125HN-C18 | ADC1015S125HN/C1 | ADC1210S065HN/C1 | ADC10D020CIVSX/NOPB |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | Texas Instruments |
| Package | 56-HVQFN exposed pad (8x8 mm) | 56-HVQFN exposed pad (8x8 mm) - same | 56-HVQFN exposed pad (8x8 mm) - same | 56-HVQFN exposed pad (8x8 mm) - same | 56-HVQFN exposed pad (8x8 mm) - same | VQFN-48 (CROSS-PACKAGE, requires PCB rework) |
| Resolution | 12 bit | 12 bit | 12 bit | 10 bit | 12 bit | 10 bit |
| Number of Channels | 2 | 2 | 1 | 1 | 1 | 2 |
| Max Sample Rate | 125 Msps | 80 Msps | 125 Msps | 125 Msps | 65 Msps | 20 Msps |
| Analog Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 3.3 V (CROSS-PACKAGE note) |
| Data Interface | JESD204A (subclass 0), 2 lanes up to 1.25 Gbps | JESD204A (subclass 0), 2 lanes | JESD204A (subclass 0), 2 lanes | JESD204A (subclass 0), 1 lane | JESD204A (subclass 0), 1 lane | Parallel LVCMOS (CROSS-PACKAGE note) |
| Automotive Grade (AEC-Q100) | No | No | Yes | No | No | No |
| Estimated Unit Price at qty 1 (USD) | 48.50 | Lower (slower speed grade) | Slightly higher (AEC-Q100 upscreen) | Lower (single channel) | Lower (single channel, slower) | Lower (different package/architecture) |
Key Differentiators
- Dual matched pipelines at full 125 Msps with shared clock and reference (vs ADC1015S125HN/C1)
- Higher sample rate at the same JESD204A bandwidth envelope (vs ADC1213D080HN/C1/5)
- AEC-Q100 qualified variant available in same footprint for chassis/automotive nodes (vs Non-automotive ADC1213D125HN-C1 itself)
Design Notes
Estimated: At 125 Msps dual-channel operation the converter typically draws around 700 mW from its 1.8 V analog and digital rails combined. Place a 1 uF bulk plus 100 nF X7R ceramic within 2 mm of every VA and VD pin, and keep the analog/digital ground returns separated with a single tie point under the exposed thermal pad. A clean LDO such as a 0.5 A drop-in is sufficient; avoid sharing the input rail with switching nodes of any buck/boost converter on the same board.
Route the four JESD204A serial lanes (DOUT0_P/N, DOUT1_P/N) and the CLKP/N clock as 100 Ω differential pairs with matched lengths to within 5 ps; the SYNC pair is LVDS-like and treated likewise. Place AC-coupling capacitors within 3 mm of the transmit pins to comply with the JESD204A specification. The exposed thermal pad must be soldered to a 4-layer PCB with at least 4 by 4 cm of contiguous inner copper pour to keep θJA close to the datasheet figure of approximately 25 C/W.
Do not leave the input common-mode voltage floating - configure the VCM pins and bias the transformer secondary or driver op-amp to that voltage, otherwise harmonic distortion and SFDR drift sharply. Per-channel gain/offset registers must be reloaded after PD toggling, or the conversion will start with non-default scaling. When running in 105 or 80 Msps modes, regenerate the FPGA JESD204A core parameters to match the new lane rate, otherwise the receiver will see an unmatched LMF profile and never complete ILAS.
Maintain a gap of 4 trace widths between analog input pairs (INxA_P/N, INxB_P/N) and the digital serial lanes; use a guard via fence on the analog side to keep common-mode switching noise from coupling into the front-end sample-and-hold. The differential input traces should be tightly coupled (5 mil gap for 100 Ω differential on FR4), while the digital serial lanes should be loosely coupled and length-tuned. Source: NXP/IDT ADC1213D datasheet evaluation board layout recommendation.
Driven from a low-jitter clock source, the ADC's SNR at 70 MHz IF is dominated by aperture jitter rather than thermal noise. Plan for a clock with sub-200 fs RMS jitter, route the clock pair as 100 Ω differential, and terminate the receiver side with a precision 100 Ω resistor if the FPGA CLKP/N does not provide internal differential termination. The SYSREF signal should be DC-balanced and one-shot pulsed; AC coupling degrades the timing window.
Compliance Information
RoHS compliant per NXP/IDT product family datasheet. Not AEC-Q100 qualified in the base -C1 variant; choose ADC1112D125HN-C18 for automotive upscreen. Halogen-free status not stated in the distributor snippets provided.
