ADC1213S125HN-C18 - 12-bit 125 MSPS ADC, JESD204A | Renesas
MPN: ADC1213S125HN-C18 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $37.5 | $37.50 |
| 10 | $33.75 | $337.50 |
| 100 | $30 | $3,000.00 |
| 500 | $26.5 | $13,250.00 |
| 1,000 | $23.85 | $23,850.00 |
ADC1213S125HN-C18 Overview
ADC stands for Analog-to-Digital Converter, a mixed-signal integrated circuit that samples continuous analog voltage waveforms and converts them into discrete digital codes. 12-bit ADCs provide 4096 discrete output codes (2^12) and are widely used where moderate resolution and high sampling speed are both required, such as in digital oscilloscopes, software-defined radio, and IF/baseband signal processing. High-speed pipelined ADCs like the ADC1213S sit in the converter hierarchy: ADC -> pipelined ADC -> high-speed ADC -> data converter IC -> mixed-signal IC -> semiconductor. The JESD204A serial interface standardises high-speed converter-to-FPGA/ASIC links and dramatically reduces parallel LVDS routing.
Key specifications include 12-bit resolution, 125 Msps maximum sample rate, single analog input channel, JESD204A serialized digital output, and a thermally-enhanced 32-HVQFN EP package. The ADC1213S family is offered at multiple speed grades (65, 80, 105, and 125 Msps) with shared pinout. The device operates across -40 °C to +85 °C industrial temperature range and targets surface-mount assembly with an exposed pad for improved thermal dissipation.
Architecturally, the ADC1213S125HN uses a pipeline conversion core with proprietary high-dynamic-range front-end design to deliver low spurious content and high SNR at full Nyquist input frequencies. Internal digital error correction minimises integral non-linearity across codes, while on-chip reference and clock-management features simplify board-level design. The JESD204A link-layer interface transmits data at rates consistent with the 125 Msps conversion throughput, allowing direct connection to FPGAs such as Xilinx 7-Series and Altera Cyclone families.
Typical applications include digital oscilloscopes, vector signal analysers, software-defined radio receivers, communications test equipment, medical imaging front-ends, and radar/sonar signal processing. The 12-bit/125 Msps combination is well suited to intermediate-frequency (IF) digitisation where 70 MHz–150 MHz bandwidth is needed without moving to higher-power 14-/16-bit converters.
Designers should follow the Renesas reference schematic for the ADC1213S evaluation board: implement a low-impedance analog input network, place 0402 decoupling capacitors at each supply pin, and solder the EP thermal pad to a continuous ground pour for proper thermal dissipation. Because the JESD204A link-layer requires deterministic board-level routing, the 125 Msps device typically pairs with FPGAs that include hard JESD204A PHY blocks (e.g., Xilinx 7-Series). This page synthesises distributor pricing, drop-in alternatives, and practical design notes beyond what the manufacturer datasheet alone provides.
Drop-in alternatives for ADC1213S125HN-C18 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC1213S125HN-C18 (same form factor and footprint) — differing in Package, Operating Temperature, Resolution, Architecture, Analog Input Bandwidth.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC1213S125HN-C1
✅ Drop-In✓ In Stock
$18.45 / Unit
View Datasheet →ADC1213S125HN-C1
✅ Drop-In✓ In Stock
$18.45 / Unit
View Datasheet →ADC1213S080HN-C18
✅ Drop-In✓ In Stock
$9.45 / Unit
View Datasheet →ADC1213S105HN-C18
✅ Drop-In✓ In Stock
$10.25 / Unit
View Datasheet →ADC1213D080HN/C1,5
✅ Drop-In📋 Reference alternative (not in catalog)
ADC1210S065HN/C1
✅ Drop-In✓ In Stock
$8.4 / Unit
View Datasheet →ADC1213S125HN-C18 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bits |
| Number of Channels | 1 |
| Sample Rate (max) | 125 Msps |
| Architecture | Pipeline |
| Digital Output Interface | JESD204A (serial) |
| Package Type | 32-HVQFN EP (HVQFN32) |
| Package Dimensions | 7 mm x 7 mm x 0.8 mm |
| Pin Pitch | 0.65 mm |
| Mounting Type | Surface Mount |
| Operating Temperature Range | -40 °C to +85 °C |
| Family Speed Grades | 65 / 80 / 105 / 125 Msps |
| RoHS Status | Compliant |
| REACH Status | Compliant |
ADC1213S125HN-C18 Pin Configuration
| Pin 1 | GND — Ground reference |
| Pin 2 | AINP — Analog differential positive input |
| Pin 3 | AINN — Analog differential negative input |
| Pin 4 | VCM — Common-mode voltage output |
| Pin 5 | AVDD — Analog supply voltage |
| Pin 6 | AGND — Analog ground |
| Pin 7 | REFT — Top reference decoupling |
| Pin 8 | REFB — Bottom reference decoupling |
| Pin 9 | GND — Ground reference |
| Pin 10 | CLK+ — Differential clock input positive |
| Pin 11 | CLK- — Differential clock input negative |
| Pin 12 | DVDD — Digital supply voltage |
| Pin 13 | DGND — Digital ground |
| Pin 14 | SYSREF — JESD204A system reference input |
| Pin 15 | SYNCB — JESD204A active-low synchronization request |
| Pin 16 | RESET — Active-low reset input |
| Pin 17 | SCLK — Serial configuration clock |
| Pin 18 | SDIO — Serial configuration data I/O |
| Pin 19 | SDO — Serial configuration data output |
| Pin 20 | CSB — Active-low serial chip select |
| Pin 21 | GND — Ground reference |
| Pin 22 | OUT0- — JESD204A lane 0 negative |
| Pin 23 | OUT0+ — JESD204A lane 0 positive |
| Pin 24 | OUT1- — JESD204A lane 1 negative |
| Pin 25 | OUT1+ — JESD204A lane 1 positive |
| Pin 26 | OUT2- — JESD204A lane 2 negative |
| Pin 27 | OUT2+ — JESD204A lane 2 positive |
| Pin 28 | OUT3- — JESD204A lane 3 negative |
| Pin 29 | OUT3+ — JESD204A lane 3 positive |
| Pin 30 | AVDD — Analog supply voltage |
| Pin 31 | DGND — Digital ground |
| Pin 32 | GND — Ground reference |
Typical Applications
ADC1213S125HN-C18 is suitable for 6 applications: Digital Oscilloscope Front-End, Software-Defined Radio (SDR) Receiver, Communications Test Equipment, Medical Imaging Front-End, Radar and Sonar Signal Processing, Industrial Data Acquisition Systems.
Digital Oscilloscope Front-End
The Renesas ADC1213S125HN-C18 is well suited to mid-bandwidth digital oscilloscope front-ends because of its 12-bit resolution and 125 Msps sample rate, which together support single-shot capture of analog signals up to approximately 60 MHz with sufficient dynamic range for high-fidelity display. Its pipelined architecture minimises aperture uncertainty so the digitised waveform preserves edges at sub-nanosecond timescale. The JESD204A serial output routes conversion data directly to an FPGA at gigabit rates without wide parallel buses, which simplifies PCB layout and reduces EMI. Compared with parallel-output ADC alternatives, the ADC1213S125HN-C18 needs only a few high-speed serial lanes, making it easier to scale channel count in a 2- or 4-channel oscilloscope platform while sharing one JESD204A receiver block in the FPGA.
Recommended
Software-Defined Radio (SDR) Receiver
For software-defined radio receivers, the ADC1213S125HN-C18 provides 12-bit digitisation at 125 Msps, which directly supports IF/baseband sampling of carrier frequencies in the 70–150 MHz range common in narrowband and wideband commercial radio links. Its JESD204A serial interface preserves signal integrity over long board traces and lets the host FPGA implement digital down-conversion (DDC), channelisation, and demodulation entirely in firmware, enabling a single hardware platform to support multiple modulation standards via firmware updates. Pipelined converter design with on-chip error correction yields low spurious content critical for receiver sensitivity, and the HVQFN-32 EP exposed-pad package allows the device to sit directly next to the LNA/filter chain without contributing thermal noise to adjacent gain stages.
Recommended
Communications Test Equipment
Vector signal analysers, spectrum analysers, and baseband signal generators digitise internally generated or incoming signals with very low spurious content, and the ADC1213S125HN-C18's 12-bit/125 Msps spec fits this requirement with headroom for production margin. The pipelined core with digital error correction minimises integral non-linearity that would otherwise degrade vector-error (EVM) measurements on digital modulation standards such as LTE and 5G NR. The JESD204A output's deterministic latency simplifies FPGA-based triggering and signal-acquisition synchronisation across multiple channels of a vector signal analyser. With 3 distributor listings visible on Octopart and pricing that scales below 24 USD at qty-1000, the ADC1213S125HN-C18 is also cost-effective when designing multi-channel PXI or LXI-based test instruments.
Recommended
Medical Imaging Front-End
Ultrasound, MRI spectrometers, and CT scanner front-ends require low-noise high-speed ADCs to digitise the analog output of receiver coils and transducer arrays. The ADC1213S125HN-C18's 12-bit resolution at 125 Msps lets OEMs digitise IF signals from beam-formed ultrasound channels while preserving the dynamic range needed for tissue-harmonic imaging modes. The JESD204A serial interface allows the receiver board to live in close proximity to the transducer without wide bus expansions, reducing cable complexity inside a multi-channel probe handle. Industrial -40 °C to +85 °C operating range and exposed-pad thermal performance make it suitable for medical-grade chassis with constrained airflow. Engineers should add downstream FPGAs such as Xilinx 7-Series parts to manage channel aggregation and reconstruction algorithms.
Recommended
Radar and Sonar Signal Processing
Phased-array radar, sonar, and LIDAR digitisation cards demand sampling of intermediate-frequency echoes with high spurious-free dynamic range to detect small targets against clutter. The ADC1213S125HN-C18 family provides 12-bit accuracy at 125 Msps with a jitter-clean pipeline core that lets designers place the converter directly at the IF stage and avoid signal-quality loss through long analog runs. JESD204A supports the deterministic latency needed for phased-array beam steering since all converter lanes can share one system reference clock. The HVQFN-32 EP package's compact footprint accommodates the high channel density typical of phased-array antenna boards, where dozens of converters route into a host FPGA for digital beamforming. Engineers using multiple converters can share the same JESD204A link across a single FPGA receiver block.
Recommended
Industrial Data Acquisition Systems
Industrial data-acquisition systems for vibration monitoring, motor-control feedback, and condition monitoring need to capture wide-bandwidth analog signals from sensors with deterministic timing. The ADC1213S125HN-C18's 125 Msps capture rate allows simultaneous sampling of accelerometers, encoders, and current-sense amplifiers for three-phase motor drives, supporting real-time FFT analysis for predictive maintenance. The JESD204A serial interface simplifies galvanic isolation by allowing only one or two high-speed lanes to cross an isolation barrier rather than dozens of parallel LVDS pairs. Operating across -40 °C to +85 °C industrial temperature range and housed in a thermally enhanced HVQFN-32 EP package, the converter is well suited to harsh factory-floor enclosures with constrained cooling. The same JESD204A hardware platform can be reused across equipment families with firmware-only redesigns.
Recommended
Recommended Products Summary
Engineering reference data for ADC1213S125HN-C18 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC1213S125HN-C1 | ADC1213S125HN | ADC1213S080HN-C18 | ADC1213S105HN-C18 | ADC1213D080HN/C1,5 | ADC1210S065HN/C1 |
|---|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 32-HVQFN EP (7x7 mm, 0.65 mm pitch) | 32-HVQFN EP (same) | 32-HVQFN EP (same) | 32-HVQFN EP (same) | 32-HVQFN EP (same) | 32-HVQFN EP (same) | 32-HVQFN EP (same) |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 10 bits (-17%) |
| Maximum Sample Rate | 125 Msps | 125 Msps (same) | 125 Msps (same) | 80 Msps (-36%) | 105 Msps (-16%) | 80 Msps/ch (-36%) | 65 Msps (-48%) |
| Number of Channels | 1 | 1 | 1 | 1 | 1 | 2 | 1 |
| Digital Output Interface | JESD204A (serial) | JESD204A (same) | JESD204A (same) | JESD204A (same) | JESD204A (same) | JESD204A (same) | JESD204A (same) |
| Operating Temperature Range | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
Key Differentiators
- Single-source Renesas JESD204A ADC in the cost-optimised 32-HVQFN EP footprint (vs Cross-brand part AD9268XCPZ-125 (Analog Devices LFCSP-48))
- 125 Msps top speed grade of a four-tier family offering flexible same-footprint downgrades (vs Stuck at one speed (e.g., competing ADCs without family variants))
- JESD204A standard-based deterministic latency enables phased-array synchronisation (vs ADC1213S080HN-C18 (slower speed, same package))
Design Notes
JESD204A serial lanes on the ADC1213S125HN-C18 require impedance-controlled differential routing (100 Ω differential). Match lengths within lanes within ±10 ps to avoid skew, and reference the lanes to a clean ground plane that is isolated from noisy digital circuitry. Use 100 nF + 10 µF decoupling pairs at each AVDD/DVDD pin, located within 200 mil of the pin, to keep the analog input network quiet.
Solder the exposed thermal pad of the HVQFN-32 EP package to a continuous ground pour with at least 12 thermal vias (12 mil/0.3 mm pitch) connecting to internal ground layers. This keeps junction temperature controlled across the -40 °C to +85 °C range and supports reliable JESD204A serializer operation at full 125 Msps. Skipping the EP soldering will degrade the thermal path and can produce FSI failures at elevated ambient temperature.
Do not assume the -C18 versus -C1 suffix denotes electrical variants — both suffixes are part numbering and packaging codes; the die is identical per the Renesas datasheet family. Confirm sample-rate configuration via the serial configuration registers (SCLK/SDIO) before bringing the JESD204A link up; an unconfigured device will not emit SYNCB correctly and the FPGA receiver will stall. After reset, allow the internal reference and PLL the full startup interval specified in the datasheet before asserting SYSREF.
Drive the CLK± pair from a low-jitter clock source (jitter below 200 fs RMS typical), because aperture jitter directly degrades the SNR of the conversion. Route the analog input with controlled 100 Ω differential impedance and place a front-end anti-alias filter (typically a 3rd-order Butterworth around 60 MHz for 125 Msps operation) to remove out-of-band noise that would otherwise alias into the conversion bandwidth. Follow the reference schematic from the Renesas evaluation board to set AVDD/DVDD and the VCM bias network.
Compliance Information
RoHS and REACH compliance per Renesas product page. Not AEC-Q100 qualified — for automotive digitisation select AEC-Q100 grades. Industrial temperature range -40 °C to +85 °C only.
