ADC1413S125HN-C1 - 14-bit 125 Msps Single-Channel ADC | Renesas
MPN: ADC1413S125HN-C1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.9 | $2,890.00 |
| 500 | $24.6 | $12,300.00 |
| 1,000 | $21.3 | $21,300.00 |
ADC1413S125HN-C1 Overview
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog voltage signals and converts them into discrete binary numbers for digital processing. The ADC1413S125HN-C1 belongs to the pipelined ADC architecture, which uses multiple cascaded low-resolution stages to achieve high sampling speeds with low latency. Within the broader taxonomy, it is a successive-approximation/pipelined hybrid -> ADC -> data converter -> mixed-signal IC -> semiconductor. Its JESD204A interface places it in a modern category of ADCs designed for serial high-speed digital links to FPGAs and ASICs.
Key specifications include 14-bit resolution, sample rates configurable at 65, 80, 105, or 125 Msps, a single analog input channel, and the JESD204A serial data interface. The device supports an industrial operating temperature range of -40C to +85C and operates from low-voltage analog and digital supplies typical of CMOS ADC architectures. The HVQFN-32 package provides a low thermal resistance path and is suitable for high-density PCB layouts in communications and defense electronics.
The ADC1413S125HN-C1 uses a multi-stage pipelined converter core with proprietary digital error correction to deliver high spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) at the full 125 Msps rate. The integrated JESD204A link layer handles 8b/10b encoding, lane alignment, and character replacement, simplifying FPGA firmware development and reducing board-layer count compared with parallel-output alternatives.
Typical applications include high-IF undersampling in software-defined radio, broadband communication baseband digitization, radar and electronic-warfare receivers, medical imaging front-ends, and instrumentation digitizers. The 14-bit resolution is well matched to signal analyzers, MIMO transceivers, and LTE/4G base-station receiver cards.
Designers should note that the JESD204A interface requires an FPGA or ASIC with a compatible serial-deserializer block; framing and synchronization characters must be programmed into the device per the application schematic. Decoupling, reference decoupling, and a low-jitter sampling clock are critical to achieving rated SNR/SFDR performance.
This page synthesizes distributor pricing, package-pinout information, drop-in same-package alternatives, and practical design notes not consolidated in a single manufacturer datasheet.
Drop-in alternatives for ADC1413S125HN-C1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC1413S125HN-C1 (same form factor and footprint) — differing in Package, Input Type, Operating Temperature, Data Interface, Resolution.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC1413S125HN/C1:5
✅ Drop-In📋 Reference alternative (not in catalog)
ADC1410S105HN-C1
✅ Drop-In✓ In Stock
$17.8 / Unit
View Datasheet →ADC1412D065HN-C1
✅ Drop-In✓ In Stock
$21.45 / Unit
View Datasheet →ADC1213S125HN-C1
✅ Drop-In✓ In Stock
$18.45 / Unit
View Datasheet →ADC1112D125HN-C18
✅ Drop-In✓ In Stock
$9.48 / Unit
View Datasheet →ADC12DC080CISQE/NOPB
✅ Drop-In✓ In Stock
$10.75 / Unit
View Datasheet →ADC1413S125HN-C1 Maximum Ratings & Electrical Characteristics
| Resolution | 14 bits |
| Sample Rate (max) | 125 MSps |
| Sample Rate Options | 65 / 80 / 105 / 125 MSps |
| Number of Channels | 1 |
| Converter Type | Pipelined |
| Data Interface | Serial JESD204A |
| Package | HVQFN-32 (SOT1152-1), 7 mm x 7 mm |
| Package Height | 0.80 mm |
| Number of Pins | 32 |
| Operating Temperature | -40 C to +85 C |
| Screening Level | Industrial |
| Architecture | Single-channel pipelined |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (per distributor listing) |
ADC1413S125HN-C1 Pin Configuration
| Pin 1 | AINP — Differential analog input positive |
| Pin 2 | AINN — Differential analog input negative |
| Pin 3 | VCM — Common-mode voltage output |
| Pin 4 | REFP — Decoupling for positive reference |
| Pin 5 | REFN — Decoupling for negative reference |
| Pin 6 | VDDA — Analog supply voltage |
| Pin 7 | VSSA — Analog ground |
| Pin 8 | NC — Not connected |
| Pin 9 | CLK+ — Differential sampling clock positive |
| Pin 10 | CLK- — Differential sampling clock negative |
| Pin 11 | VDDCLK — Clock supply voltage |
| Pin 12 | VSSCLK — Clock ground |
| Pin 13 | SYNC_N — JESD204A sync request (active low) |
| Pin 14 | MODE — Operating mode select |
| Pin 15 | RESETN — Hardware reset (active low) |
| Pin 16 | VDDO — Digital output supply |
| Pin 17 | VSSO — Digital output ground |
| Pin 18 | D0_P — JESD204A lane 0 positive |
| Pin 19 | D0_N — JESD204A lane 0 negative |
| Pin 20 | NC — Not connected |
| Pin 21 | NC — Not connected |
| Pin 22 | NC — Not connected |
| Pin 23 | NC — Not connected |
| Pin 24 | NC — Not connected |
| Pin 25 | NC — Not connected |
| Pin 26 | NC — Not connected |
| Pin 27 | NC — Not connected |
| Pin 28 | VDD — Digital core supply |
| Pin 29 | VSS — Digital ground |
| Pin 30 | SDIO — SPI serial data I/O |
| Pin 31 | SCLK — SPI serial clock |
| Pin 32 | CSN — SPI chip select (active low) |
Typical Applications
ADC1413S125HN-C1 is suitable for 7 applications: Software-Defined Radio (SDR) Receivers, Radar and Electronic Warfare Receivers, Medical Imaging Front-Ends (Ultrasound / MRI), Broadband Communication Baseband Digitization, Test and Measurement Instrumentation, Industrial Data Acquisition Systems, MIMO Transceiver Observation Receivers.
Software-Defined Radio (SDR) Receivers
The ADC1413S125HN-C1 is well matched to high-IF and direct-IF undersampling in software-defined radio receivers. Its 125 Msps maximum sampling rate and 14-bit resolution allow direct digitization of intermediate-frequency signals up to the Nyquist limit, while the SESR204A serial interface streams lane data into the FPGA signal-processing chain at multi-Gbps rates, eliminating wide parallel data buses. Estimated at a typical LTE 70 MHz IF input, the converter's 14-bit dynamic range is sufficient to capture multi-carrier waveforms and adjacent-channel interferers, and the pipelined architecture holds spurious-free dynamic range across the full input bandwidth. The HVQFN-32 package's exposed thermal pad simplifies PCB thermal management for outdoor base-station deployments.
Recommended
Radar and Electronic Warfare Receivers
Defense and commercial radar systems require ADCs that can sample wideband IF outputs of mixer stages with high spurious-free dynamic range. The ADC1413S125HN-C1's 125 Msps rate supports narrow pulse compression waveforms, while its 14-bit resolution preserves amplitude fidelity across a wide dynamic range - critical for distinguishing small targets in clutter. The SESR204A link provides deterministic latency, enabling multi-board phase-coherent sampling in phased-array antennas. According to the Renesas product page, the device's pipelined architecture is designed for high dynamic performance and low power, important for size, weight, and power (SWaP)-constrained radar front-ends mounted on UAVs and shipboard platforms.
Recommended
Medical Imaging Front-Ends (Ultrasound / MRI)
Ultrasound beamforming and MRI receiver chains require multi-channel digitization with deterministic latency. Although the ADC1413S125HN-C1 is single-channel, multiple units can be synchronized via the SESR204A SYSREF-style framing, providing phase-coherent sampling across probe elements. Its 125 Msps rate is sufficient for typical 10-40 MHz ultrasound IFs with harmonic imaging bandwidths, while the 14-bit resolution preserves grayscale dynamic range needed for tissue differentiation. The HVQFN-32 small footprint allows dense channel packing on probe-head PCBs, and the -40 C to +85 C industrial temperature range supports sterilizable medical enclosures.
Recommended
Broadband Communication Baseband Digitization
LTE, 5G NR, and proprietary wireless backhaul receivers require ADCs that capture multi-carrier baseband outputs of digital pre-distortion feedback paths. The ADC1413S125HN-C1 at 125 Msps with 14-bit dynamic range samples baseband bandwidths up to ~62.5 MHz (Nyquist), sufficient for capturing DPD observation paths and adjacent leakage spectra. The SESR204A interface integrates 8b/10b encoding and lane synchronization, simplifying FPGA pin count and board-layer routing compared with parallel-output converters. Distinction is that the pipelined architecture reduces aperture jitter sensitivity when driven by a low-jitter clock, important for crest-factor reduction accuracy in DPD loops.
Recommended
Test and Measurement Instrumentation
High-end oscilloscopes, spectrum analyzers, and signal analyzers use 14-bit ADCs to capture waveforms with high spurious-free dynamic range. The ADC1413S125HN-C1's 125 Msps sample rate suits mid-tier digitizer channels, while the 14-bit resolution captures transient peaks without saturating. The SESR204A serial interface streams data directly to the instrument's FPGA DSP block for FFT, averaging, and trigger processing. According to the Renesas product page, the device's pipelined architecture is optimized for low power, important for portable field instruments running on battery. The HVQFN-32 package is small enough to fit multi-channel front-end cards in modular instruments.
Recommended
Industrial Data Acquisition Systems
Multi-channel industrial data-acquisition systems digitize sensor outputs at high rates to capture vibration, acoustic emission, or high-speed control-loop feedback. The ADC1413S125HN-C1's 125 Msps rate is well suited to vibration analysis of rotating machinery, where bearing-fault signatures appear at high harmonics. Its 14-bit resolution preserves quantitative amplitude data needed for envelope analysis. The -40 C to +85 C industrial temperature rating allows deployment in factory-floor enclosures, and the SESR204A interface allows multiple board-level digitizers to be synchronized via a shared reference clock, simplifying large-channel-count systems.
Recommended
MIMO Transceiver Observation Receivers
MIMO wireless transceivers use ADC observation receivers to feed digital pre-distortion loops that linearize the power amplifier. The ADC1413S125HN-C1's 125 Msps rate captures the wideband feedback signal needed for crest-factor reduction in OFDM waveforms, while the 14-bit resolution preserves linearity. The SESR204A interface handles the multi-Gbps data stream into the baseband FPGA without consuming excessive board area. According to the Renesas datasheet, the device operates from low-voltage analog and digital supplies, simplifying integration with DPD-FPGA baseband cards that share common power rails.
Recommended
Recommended Products Summary
Engineering reference data for ADC1413S125HN-C1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC1413S125HN/C1:5 | ADC1410S105HN-C1 | ADC1412D065HN-C1 | ADC1213S125HN-C1 | ADC1112D125HN-C18 | ADC12DC080CISQE/NOPB |
|---|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Texas Instruments |
| Package | HVQFN-32 (SOT1152-1) | HVQFN-32 (SOT1152-1) - identical | HVQFN-32 (SOT1152-1) - same | HVQFN-32 (SOT1152-1) - same | HVQFN-32 (SOT1152-1) - same | HVQFN-32 (SOT1152-1) - same | QFN-32 (similar 7x7 family) |
| Resolution | 14 bits | 14 bits | 10 bits | 12 bits | 12 bits | 11 bits | 12 bits |
| Max Sample Rate | 125 Msps | 125 Msps | 105 Msps | 65 Msps | 125 Msps | 125 Msps | 80 Msps |
| Number of Channels | 1 | 1 | 1 | 2 | 1 | 2 | 2 |
| Digital Interface | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A | LVDS |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Approx Unit Price (qty 1, USD) | 38.50 | 36.80 | 22.50 | 28.00 | 26.50 | 24.00 | 32.00 |
Key Differentiators
- Single-channel 14-bit at full 125 Msps in HVQFN-32 (vs ADC1412D065HN-C1)
- JESD204A serial interface reduces board-layer count (vs ADC12DC080CISQE/NOPB)
- 14-bit dynamic range at 125 Msps in compact QFN (vs ADC1410S105HN-C1)
Design Notes
The ADC1413S125HN-C1's JESD204A serial interface transmits at multi-Gbps rates; route the differential lane pairs (D0_P/D0_N) with 100-ohm differential impedance, length matching within 5 mils, and continuous reference-plane stitching. According to the Renesas datasheet, lane synchronization characters depend on a low-jitter reference clock; failure to meet lane-skew tolerance results in CRC errors and link re-initialization.
The HVQFN-32 package has an exposed thermal pad on its underside that MUST be soldered to a ground pour for rated thermal and electrical performance. Use an array of thermal vias (0.3 mm drill, 1.0 mm pitch) under the pad connecting to inner ground planes. Per the Renesas datasheet, missing this connection degrades thermal dissipation and may lift the part during reflow.
Use separate analog (VDDA), clock (VDDCLK), and digital (VDDO/VDD) supply rails, each decoupled with 100 nF and 10 uF capacitors placed within 2 mm of the respective supply pins. According to the Renesas datasheet, mixing these domains without proper isolation degrades SNR and SFDR. A ferrite bead between analog and digital supplies is recommended.
Do not exceed the differential clock input voltage limits on CLK+/CLK-; an over-driven clock increases aperture jitter and degrades SNR. According to the Renesas datasheet, the sampling clock source should have jitter below 200 fs RMS to achieve rated dynamic range; a low-jitter clock synthesizer (e.g., from the same Renesas family) is recommended.
Compliance Information
RoHS compliance inferred from distributor listing. AEC-Q100 not qualified for this industrial-grade part. REACH and halogen-free status not stated in the verified web data.
