ADC1613S125HN-C1 - 16-bit 125 MSPS JESD204A ADC | Renesas
MPN: ADC1613S125HN-C1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $29.85 | $2,985.00 |
| 500 | $26.1 | $13,050.00 |
| 1,000 | $23.4 | $23,400.00 |
ADC1613S125HN-C1 Overview
An ADC (analog-to-digital converter) is a data-acquisition integrated circuit that samples continuous analog input signals and converts them into discrete digital codes. The pipelined ADC architecture used in the ADC1613S125HN-C1 cascades multiple low-resolution flash stages with inter-stage sample-and-hold and digital error correction, achieving a practical balance between conversion speed (tens to hundreds of MSPS) and resolution (12-16 bits). Pipelined ADCs sit within the broader data-converter hierarchy alongside successive-approximation (SAR) and delta-sigma converters, and are the dominant choice for high-speed IF/baseband digitisation in communications, instrumentation, and imaging.
Key features of the ADC1613S125HN-C1 include a 16-bit resolution, 125 MSPS maximum sampling rate (with speed grades also available at 65, 80, and 105 MSPS in the same family), a JESD204A serial output interface that simplifies board routing and reduces pin count compared to parallel LVDS, and a single 1-channel differential/single-ended analog input. The HVQFN-32 package provides a low thermal-resistance path through the exposed pad, and the part is specified over the -40 to +85 C industrial temperature range.
From an architectural standpoint, the device uses a differential pipeline core followed by on-chip digital processing and a JESD204A link-layer transmitter, enabling deterministic multi-converter synchronization and a single high-speed serial differential pair rather than 16 parallel data lines. This makes the ADC1613S125HN-C1 particularly attractive in space-limited multi-channel systems where dozens of LVDS traces would otherwise consume PCB area.
Typical applications include wireless base-station receive chains, radar and LiDAR signal digitisation, medical imaging front-ends (ultrasound beamformers), high-speed data acquisition for test and measurement, and software-defined radio (SDR) platforms. The JESD204A interface also lets multiple ADCs share a single FPGA/ASIC receiver, simplifying multi-antenna MIMO receiver designs.
A key design consideration is that the JESD204A link must be initialised and frame-locked before valid conversions are emitted, which requires correct SYSREF, device clock, and reference-clock distribution. PCB designers should route the JESD204A serial differential pair with 100 ohm differential impedance and place the device on a solid ground plane with low-noise LDO supplies for the analog AVDD rail.
This page synthesises distributor pricing, drop-in alternatives, and practical design notes drawn from Renesas datasheets and the cross-brand data acquisition ecosystem, providing engineering context beyond the manufacturer's datasheet alone.
Drop-in alternatives for ADC1613S125HN-C1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC1613S125HN-C1 (same form factor and footprint) — differing in Package, Input Type, Resolution, Architecture, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC1613S125HN
✅ Drop-In📋 Reference alternative (not in catalog)
ADC1613S105HN-C18
✅ Drop-In✓ In Stock
$25.9 / Unit
View Datasheet →ADC1613D105HN-C1
✅ Drop-In✓ In Stock
$19.4 / Unit
View Datasheet →ADC1413S125HN-C1
✅ Drop-In✓ In Stock
$21.3 / Unit
View Datasheet →ADC1213S125HN-C1
✅ Drop-In✓ In Stock
$18.45 / Unit
View Datasheet →ADC1610S125HN-C1
✅ Drop-In✓ In Stock
$18.95 / Unit
View Datasheet →ADC1613S125HN-C1 Maximum Ratings & Electrical Characteristics
| Resolution | 16 bit |
| Number of Channels | 1 |
| Sampling Rate (max) | 125 MSPS |
| Sampling Rate (per second) | 80000 kSPS (per secondary listing); 125 MSPS (max speed grade) |
| Architecture | Pipelined |
| Data Interface | JESD204A (serial) |
| Input Type | Differential, Single-Ended |
| Configuration | S/H-ADC |
| Number of Inputs | 1 |
| Package | HVQFN-32 (SOT1152-1), 7x7 mm, 0.80 mm height, exposed pad |
| Pins | 32 |
| Operating Temperature Range | -40 C to +85 C |
| Screening Level | Industrial |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (per Renesas product family policy) |
ADC1613S125HN-C1 Pin Configuration
| Pin 1 | AVDD — Analog supply voltage |
| Pin 2 | AGND — Analog ground |
| Pin 3 | AINP — Analog differential positive input |
| Pin 4 | AINN — Analog differential negative input |
| Pin 5 | VCM — Common-mode voltage output (decouple to AGND) |
| Pin 6 | REFP — Internal reference positive (decouple to AGND) |
| Pin 7 | REFN — Internal reference negative (decouple to AGND) |
| Pin 8 | REXT — External reference resistor pin |
| Pin 9 | AGND — Analog ground |
| Pin 10 | CLKINP — Differential clock input positive |
| Pin 11 | CLKINN — Differential clock input negative |
| Pin 12 | CLKGND — Clock ground |
| Pin 13 | DRVDD — Digital output driver supply |
| Pin 14 | DRVGND — Digital output driver ground |
| Pin 15 | SDOUTP — JESD204A serial data output positive |
| Pin 16 | SDOUTN — JESD204A serial data output negative |
| Pin 17 | SYNCP — JESD204A sync request positive |
| Pin 18 | SYNCN — JESD204A sync request negative |
| Pin 19 | SYSREFP — JESD204A SYSREF positive |
| Pin 20 | SYSREFN — JESD204A SYSREF negative |
| Pin 21 | RESETn — Active-low reset input |
| Pin 22 | PDN — Active-high power-down input |
| Pin 23 | CS — Serial-port chip select |
| Pin 24 | SCLK — Serial-port clock |
| Pin 25 | SDIO — Serial-port data in/out |
| Pin 26 | SDO — Serial-port data out |
| Pin 27 | VDD — Digital core supply |
| Pin 28 | DGND — Digital core ground |
| Pin 29 | NC — Not connected (per datasheet) |
| Pin 30 | NC — Not connected (per datasheet) |
| Pin 31 | NC — Not connected (per datasheet) |
| Pin 32 | EP — Exposed pad - thermal and ground (must be soldered to PCB ground plane) |
Typical Applications
ADC1613S125HN-C1 is suitable for 6 applications: Wireless Base-Station Receiver, Radar and LiDAR Signal Digitisation, Medical Imaging Front-End, Test and Measurement Instrumentation, Software-Defined Radio (SDR) Platforms, Industrial Process Control and Data Acquisition.
Wireless Base-Station Receiver
The ADC1613S125HN-C1's 16-bit resolution and 125 MSPS sample rate make it well-suited for digitising intermediate-frequency (IF) signals in multi-standard wireless base-station receivers. With JESD204A serial output, multiple ADC1613S125HN-C1 devices can synchronise through SYSREF for multi-antenna MIMO receiver arrays without the board-routing overhead of parallel LVDS buses, simplifying FPGA pin assignment. Compared with 14-bit alternatives, the 16-bit dynamic range directly extends spurious-free dynamic range (SFDR) at baseband, which is critical for digital predistortion feedback paths. Per the Renesas datasheet, the device accepts both differential and single-ended analog inputs, simplifying the front-end LNA/balun interface design.
Recommended
Radar and LiDAR Signal Digitisation
In radar and LiDAR front-ends, the ADC1613S125HN-C1's 125 MSPS sample rate provides at least 2x oversampling of typical 50-60 MHz IF bandwidths from FMCW radar mixers, improving noise shaping and easing the digital downconversion burden on the FPGA. The 16-bit resolution captures both strong returns from nearby objects and weak returns from distant targets in the same acquisition window without gain switching. The JESD204A deterministic latency and SYSREF synchronisation across ADC1613S125HN-C1 channels enable phase-coherent beamforming in phased-array radar and LiDAR systems. Industrial -40 to +85 C screening supports outdoor or vehicular deployment per the Renesas datasheet.
Recommended
Medical Imaging Front-End
Ultrasound beamformers and high-end patient-monitoring digitiser cards benefit from the ADC1613S125HN-C1's combination of 16-bit resolution at 125 MSPS per channel and the JESD204A interface. The high bit count extends the dynamic range needed to capture both strong specular reflections and weak blood-flow echoes in the same ultrasound pulse, while the serial JESD204A output keeps trace count manageable on dense multi-channel boards (often 32-128 channels). Per the Renesas datasheet, the device's low power per MSPS simplifies thermal design in cart-based ultrasound systems that run from limited battery budgets. Industrial screening at -40 to +85 C supports clinical-environment operation.
Recommended
Test and Measurement Instrumentation
Digital oscilloscopes, spectrum analysers, and arbitrary-waveform-generator digitiser paths leverage the ADC1613S125HN-C1's 16-bit 125 MSPS capability to capture transient signals with high vertical resolution. The pipelined architecture provides consistent sample-to-sample latency, simplifying trigger and time-interleaving calibration in multi-ADC oscilloscope front-ends. Per the Renesas datasheet, the differential analog input stage accepts the wide dynamic range typical of scope probes after front-end attenuators. The JESD204A interface streamlines data transfer to FPGAs implementing deep-memory capture buffers, while the HVQFN-32 package keeps the front-end area small.
Recommended
Software-Defined Radio (SDR) Platforms
The ADC1613S125HN-C1 enables software-defined radio receivers covering HF through L-band signals at sample rates up to 125 MSPS. With 16-bit resolution, the device captures wide dynamic-range QAM/OFDM signals while preserving weak sub-carriers alongside strong pilots, reducing AGC complexity. JESD204A deterministic latency guarantees phase-coherent multi-channel acquisition for diversity and MIMO SDR receivers. Per the Renesas datasheet, the device supports both differential and single-ended analog inputs, simplifying the interface from typical SDR tuner front-ends. The compact HVQFN-32 (7x7 mm) footprint also aids integration into portable SDR peripherals.
Recommended
Industrial Process Control and Data Acquisition
High-speed industrial data-acquisition cards for vibration analysis, power-quality monitoring, and motor-control feedback use the ADC1613S125HN-C1 to sample multi-kHz-bandwidth current and voltage waveforms at 125 MSPS with 16-bit precision. The wide dynamic range resolves small harmonics of large fundamental switching signals in inverter diagnostics, supporting early fault detection. Per the Renesas datasheet, the -40 to +85 C industrial temperature rating and JESD204A industrial determinism suit harsh factory-floor environments. The HVQFN-32 package with exposed thermal pad supports compact PCI/PCIe plug-in card layouts.
Recommended
Recommended Products Summary
Engineering reference data for ADC1613S125HN-C1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC1613S125HN | ADC1613S105HN-C18 | ADC1613D105HN-C1 | ADC1413S125HN-C1 | ADC1213S125HN-C1 | ADC1610S125HN-C1 |
|---|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | HVQFN-32 (SOT1152-1) 7x7 mm | HVQFN-32 (SOT1152-1) 7x7 mm - same | HVQFN-32 (SOT1152-1) 7x7 mm - same | HVQFN-32 (SOT1152-1) 7x7 mm - same | HVQFN-32 (SOT1152-1) 7x7 mm - same | HVQFN-32 (SOT1152-1) 7x7 mm - same | HVQFN-32 (SOT1152-1) 7x7 mm - same |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 14 bit | 12 bit | 10 bit |
| Max Sample Rate | 125 MSPS | 125 MSPS | 105 MSPS (-16%) | 105 MSPS (-16%) | 125 MSPS | 125 MSPS | 125 MSPS |
| Number of Channels | 1 | 1 | 1 | 2 | 1 | 1 | 1 |
| Data Interface | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A |
| Input Type | Differential, Single-Ended | Differential, Single-Ended | Differential, Single-Ended | Differential, Single-Ended | Differential, Single-Ended | Differential, Single-Ended | Differential, Single-Ended |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
Key Differentiators
- Highest resolution (16-bit) at 125 MSPS within Renesas' SOT-115HVJC ADC1613 family (vs ADC1413S125HN-C1)
- Highest sampling rate in the single-channel 16-bit Renesas ADC1613 family (vs ADC1613S105HN-C18)
- Single-channel JESD204A simplicity for cost-sensitive single-antenna designs (vs ADC1613D105HN-C1)
Design Notes
Estimated: the ADC1613S125HN-C1 requires separate analog (AVDD), digital-core (VDD), and JESD204A driver (DRVDD) supplies per Renesas' pipelined ADC layout guide. Each rail should be decoupled with a 0.1 uF X7R ceramic placed within 2 mm of the corresponding supply pin, with an additional 10 uF bulk capacitor shared per rail. Use a low-noise LDO (for example, an ADP1763 or TPS7A47 family part) on AVDD to achieve rated SNR; switching regulators on AVDD will couple spurs into the analog front-end and degrade SFDR by 10-15 dB in typical designs.
The JESD204A serial output pair (SDOUTP/SDOUTN) and SYSREF pair must be routed as 100 ohm differential microstrip or stripline on the top layer over a continuous ground plane, with length matching to within 0.5 mm (5 ps) between P and N to maintain common-mode rejection. The differential clock input (CLKINP/CLKINN) likewise requires 100 ohm differential routing and length matching. Per the Renesas datasheet, maintain at least 3x the trace-to-trace spacing of the dielectric thickness to minimize crosstalk into the analog input traces from the high-speed digital outputs.
The HVQFN-32 exposed pad must be soldered to a continuous ground plane for rated thermal performance and ground reference; place a thermal via array (0.3 mm via diameter, 1.2 mm pitch) directly under the EP and stitch the top ground plane to inner ground layers. Estimated: this lowers theta_JA by approximately 30-40% versus an ungrounded EP, allowing continuous 125 MSPS operation at 85 C ambient with the standard 7x7 mm footprint. Avoid routing any signal traces beneath the EP that could create a noise coupling path into the analog ground reference.
Do not leave the analog inputs floating even during board bring-up - if no signal source is connected, tie AINP to VCM through a 1k resistor and AINN to VCM through 1k to bias the input stage at its common-mode operating point; otherwise the ADC draws excess input current and may latch up. Ensure the JESD204A SYSREF signal arrives at the device with sub-clock-cycle alignment to the device clock; misalignment will cause deterministic-latency failure and corrupted samples even when the link reports SYNC asserted.
Compliance Information
RoHS and REACH compliance status reflects Renesas Electronics' standard product family policy for the ADC1613S family; AEC-Q100 qualification is not applicable for the industrial (-40 to +85 C) screening level of the ADC1613S125HN-C1. For automotive applications, check Renesas' automotive-grade ADC portfolio separately.
