ADC3223IRGZ25 - Dual 12-Bit 80MSPS Low-Power ADC | Texas Instruments
MPN: ADC3223IRGZ25 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.45 | $18.45 |
| 10 | $16.78 | $167.80 |
| 100 | $14.92 | $1,492.00 |
| 500 | $13.45 | $6,725.00 |
| 1,000 | $11.98 | $11,980.00 |
ADC3223IRGZ25 Overview
A pipelined ADC is a high-speed analog-to-digital converter that resolves an analog input by cascading low-resolution flash stages with digital error correction and inter-stage residue gain. Each stage samples and holds the input, performs a coarse quantization, and passes an amplified residue to the next stage; the final code is assembled from the per-stage decisions plus latency. This architecture dominates the 10 MSPS to 500 MSPS performance window because it scales resolution, speed, and power much more favorably than flash or SAR converters. Within the power-management hierarchy, the ADC sits at the analog front-end -> data converter -> signal chain layer of mixed-signal ICs.
Key features of the ADC3223IRGZ25 include dual simultaneous-sampling 12-bit channels, an 80 MSPS sample rate, LVDS and serial CMOS interface options, integrated low-jitter clock buffer, and programmable gain. The device operates from a single 1.8 V supply and from -40C to +85C industrial temperature range. Its pipelined core delivers high spurious-free dynamic range while keeping total power below competing dual-channel ADCs in the same MSPS class.
The ADC3223 uses a switched-capacitor pipelined front-end with on-chip reference, digital calibration, and selectable output formats. The 12-bit -Q1 suffix indicates 25 MSPS operation within the broader ADC32xx family; the underlying silicon supports up to 80 MSPS at higher -speed grades. LVDS outputs minimize EMI for backplane and board-to-board digital links while CMOS serial mode simplifies low-pin-count FPGA/CPU capture.
Typical applications include communications base-station IF digitization, portable and handheld instrumentation, ultrasound beamforming front-ends, multi-channel industrial data acquisition, and radar/LiDAR front-end digitizers. The dual-channel + low-power combination is especially attractive for handheld ultrasound probes where channel count and battery life both matter.
When designing with this part, decouple AVDD/DVDD with low-ESR 0.1uF plus 10uF capacitors placed within 5 mm of each supply pin, and keep the analog input traces impedance-matched to 50 ohms with a balun if driven single-ended. The internal reference can be bypassed with a 10uF cap at REFM/REFP to minimize kick-back noise at high sample rates.
Drop-in alternatives for ADC3223IRGZ25 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC3223IRGZ25 (same form factor and footprint) — differing in Package, Resolution, Input Type, Number of Channels, Operating Temperature Range.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC3223IRGZR
✅ Drop-In📋 Reference alternative (not in catalog)
ADC3224IRGZ25
✅ Drop-In✓ In Stock
$20.4 / Unit
View Datasheet →ADC3222IRGZ25
✅ Drop-In📋 Reference alternative (not in catalog)
ADC1412D065HN-C1
✅ Drop-In✓ In Stock
$21.45 / Unit
View Datasheet →ADS62P23IRGC25
✅ Drop-In✓ In Stock
$18.85 / Unit
View Datasheet →ADS6242IRGZR
✅ Drop-In✓ In Stock
$18.25 / Unit
View Datasheet →ADC3223IRGZ25 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bit |
| Number of Channels | 2 |
| Sample Rate | 80 MSPS (this grade 25 MSPS) |
| Architecture | Pipelined |
| Input Type | Differential/Single-ended analog |
| Analog Input Range | 2 Vpp maximum |
| Supply Voltage | 1.8 V nominal |
| Digital Output Interface | LVDS / Serial CMOS |
| Operating Temperature Range | -40C to +85C (Industrial) |
| Package | 48-pin VQFN (RGZ) 7x7 mm |
| Package Code | HVQCCN (QFN, no-lead) |
| Mounting Type | Surface Mount |
| MSL Level | 3 (168 hours) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
| Terminal Form | No Lead |
ADC3223IRGZ25 Pin Configuration
| Pin 1 | AVDD — Analog supply 1.8V |
| Pin 2 | INAP — Channel A positive analog input |
| Pin 3 | INAN — Channel A negative analog input |
| Pin 4 | AVDD — Analog supply 1.8V |
| Pin 5 | VCM — Common-mode voltage output |
| Pin 6 | REFP — Positive reference decoupling |
| Pin 7 | REFM — Negative reference decoupling |
| Pin 8 | AVDD — Analog supply 1.8V |
| Pin 9 | INBP — Channel B positive analog input |
| Pin 10 | INBN — Channel B negative analog input |
| Pin 11 | AVDD — Analog supply 1.8V |
| Pin 12 | AGND — Analog ground |
| Pin 13 | SENSE — Reference configuration pin |
| Pin 14 | AGND — Analog ground |
| Pin 15 | AVDD — Analog supply 1.8V |
| Pin 16 | CLKP — Differential clock positive |
| Pin 17 | CLKN — Differential clock negative |
| Pin 18 | AVDD — Analog supply 1.8V |
| Pin 19 | RESET — Hardware reset (active low) |
| Pin 20 | SEN — Serial interface enable |
| Pin 21 | SCLK — Serial interface clock |
| Pin 22 | SDATA — Serial interface data |
| Pin 23 | SDOUT — Serial interface data output |
| Pin 24 | AGND — Analog ground |
| Pin 25 | DVDD — Digital supply 1.8V |
| Pin 26 | DGND — Digital ground |
| Pin 27 | D0+ — LVDS data bit 0 positive |
| Pin 28 | D0- — LVDS data bit 0 negative |
| Pin 29 | D1+ — LVDS data bit 1 positive |
| Pin 30 | D1- — LVDS data bit 1 negative |
| Pin 31 | DVDD — Digital supply 1.8V |
| Pin 32 | D2+ — LVDS data bit 2 positive |
| Pin 33 | D2- — LVDS data bit 2 negative |
| Pin 34 | D3+ — LVDS data bit 3 positive |
| Pin 35 | D3- — LVDS data bit 3 negative |
| Pin 36 | D4+ — LVDS data bit 4 positive |
| Pin 37 | D4- — LVDS data bit 4 negative |
| Pin 38 | D5+ — LVDS data bit 5 positive |
| Pin 39 | D5- — LVDS data bit 5 negative |
| Pin 40 | DVDD — Digital supply 1.8V |
| Pin 41 | DCLK+ — LVDS data clock positive |
| Pin 42 | DCLK- — LVDS data clock negative |
| Pin 43 | D6+ — LVDS data bit 6 positive |
| Pin 44 | D6- — LVDS data bit 6 negative |
| Pin 45 | D7+ — LVDS data bit 7 positive |
| Pin 46 | D7- — LVDS data bit 7 negative |
| Pin 47 | DVDD — Digital supply 1.8V |
| Pin 48 | PDN — Power-down (active high) |
Typical Applications
ADC3223IRGZ25 is suitable for 6 applications: Communications IF Digitization, Portable Ultrasound Beamforming, Handheld Oscilloscope and Instrumentation, Multi-Channel Industrial Data Acquisition, Radar and LiDAR Front-End Digitization, Software Defined Radio Receiver.
Communications IF Digitization
The ADC3223IRGZ25's dual 12-bit channels and 80 MSPS sample rate fit intermediate-frequency (IF) digitization in 4G LTE and 5G NR small-cell base stations where two antenna paths share one ADC. Its LVDS output minimizes EMI on backplane traces and integrates directly with FPGA baseband processors. The 1.8 V supply and sub-200 mW per channel typical power reduce thermal load on the radio unit. The 70 dB SNR typical is adequate for QAM-64 demodulation in non-massive-MIMO sectors.
Recommended
Portable Ultrasound Beamforming
In handheld ultrasound probes, the ADC3223IRGZ25's dual simultaneous-sampling channels pair with ultrasound transducer pre-amps to digitize differential return signals at 25-80 MSPS. The low power (typically <200 mW per channel) keeps probe handle thermal rise under 3C per IEC 60601 patient-contact safety. Its LVDS interface drives flex cables up to 30 cm without EMI coupling into the receive path. Multiple ADC3223s cascade on a 64-channel probe PCB to feed an FPGA beamformer.
Recommended
Handheld Oscilloscope and Instrumentation
The ADC3223IRGZ25 enables two-channel bench-top oscilloscopes and portable instrumentation where dual simultaneous sampling captures analog and trigger signals at 25-80 MSPS without an external sample-and-hold. Its 1.8 V supply fits USB-powered or battery-powered enclosures, and the small VQFN-48 footprint keeps the analog front-end under 1 square inch. The 12-bit resolution delivers 0.025% full-scale accuracy suitable for embedded debug tools and field service diagnostics.
Recommended
Multi-Channel Industrial Data Acquisition
Industrial process control and vibration monitoring systems use the ADC3223IRGZ25 to digitize two simultaneous sensor channels (accelerometer + tachometer, or strain gauge + temperature) at 25 MSPS. The 80 MSPS headroom enables decimation filtering for higher effective resolution, and the dual channel reduces BOM cost versus two separate ADCs. The industrial -40C to +85C temperature range supports factory floor and outdoor installations. LVDS outputs route to a remote FPGA over shielded twisted pair.
Recommended
Radar and LiDAR Front-End Digitization
Automotive short-range radar and LiDAR front-ends use the ADC3223IRGZ25 to digitize dual IF channels at 25-80 MSPS for chirp demodulation. The dual-channel + low-power combination fits compact sensor modules under the bumper or behind the windshield, and the 12-bit resolution is sufficient for 200 MHz bandwidth FMCW chirps. LVDS outputs drive the central ECU's FPGA across coax or flex cable. The QFN exposed pad provides thermal dissipation for 24/7 sensor operation.
Recommended
Software Defined Radio Receiver
Software-defined radio (SDR) receivers in amateur radio, spectrum monitoring, and signal intelligence use the ADC3223IRGZ25 to digitize I/Q baseband or low-IF signals directly. The dual-channel architecture captures I and Q simultaneously with matched gain and phase, eliminating I/Q imbalance that degrades image-rejection. The 80 MSPS rate supports up to 50 MHz instantaneous bandwidth, suitable for HF, VHF, and most UHF monitoring bands. LVDS data connects to an FPGA running the demodulation pipeline.
Recommended
Recommended Products Summary
Engineering reference data for ADC3223IRGZ25 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC3223IRGZR | ADC3224IRGZ25 | ADC3222IRGZ25 | ADC1412D065HN-C1 |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | VQFN-48 (RGZ) 7x7 mm | VQFN-48 (RGZ) 7x7 mm - same | VQFN-48 (RGZ) 7x7 mm - same | VQFN-48 (RGZ) 7x7 mm - same | VQFN-48 (RGZ) 7x7 mm - same |
| Resolution | 12 bit | 12 bit | 14 bit | 12 bit | 14 bit |
| Number of Channels | 2 | 2 | 2 | 1 | 1 |
| Sample Rate | 25 MSPS (80 MSPS max family) | 80 MSPS | 25 MSPS | 25 MSPS | 65 MSPS |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Digital Output | LVDS / Serial CMOS | LVDS / Serial CMOS | LVDS / Serial CMOS | LVDS / Serial CMOS | LVDS |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Automotive Grade | No (industrial) | No (industrial) | No (industrial) | No (industrial) | Yes (AEC-Q100) |
| RoHS Status | Compliant | Compliant | Compliant | Compliant | Compliant |
Key Differentiators
- Dual simultaneous-sampling channels in single 48-pin QFN (vs ADC3222IRGZ25 (single-channel))
- Industry-leading low power at 80 MSPS dual-channel (vs ADS62P23IRGC25 (125 MSPS dual 14-bit))
- Industrial temperature range with high SFDR (vs ADC1412D065HN-C1 (automotive grade))
Design Notes
Decouple each AVDD and DVDD pin with a 0.1uF X7R ceramic capacitor placed within 3 mm of the pin, plus a 10uF bulk capacitor on each supply rail. Place the bulk capacitor near the package exposed pad. Route AVDD and DVDD power planes separately to avoid digital switching noise coupling into the analog front-end. The 1.8 V supply should have less than 5 mV peak-to-peak ripple at the ADC pin.
Route the differential clock traces (CLKP/CLKN) with 100 ohm differential impedance and length matching within 0.5 mm. Keep analog input traces (INAP/INAN/INBP/INBN) symmetric and as short as possible, ideally matched within 0.2 mm to preserve common-mode rejection. Place the input anti-aliasing RC network within 5 mm of the analog input pins. Use a continuous ground plane under the analog input traces to maximize shielding.
Drive the analog inputs differentially to maximize SFDR; if a single-ended source is unavoidable, use a wideband balun (e.g., Mini-Circuits ADT1-1WT) to convert to differential. Place a 50 ohm source-terminated differential pair to absorb reflections. The common-mode voltage (VCM) output pin can bias the balun center tap to set the ADC common-mode correctly.
Do not float the SENSE pin; tie it to DVDD for the internal reference or to AGND for an external reference. Ensure the LVDS output trace length matches DCLK+/- to within 1 mm to avoid data sampling errors. The exposed thermal pad (pin 49 / paddle) must be soldered to a continuous ground plane with multiple thermal vias for adequate heat dissipation - missing this reduces reliability at high sample rates.
Compliance Information
RoHS and REACH compliant per TI product page. Industrial temperature grade (-40C to +85C); not AEC-Q100 qualified - choose ADC1412D065HN-C1 for automotive applications. Halogen-free status not explicitly stated in provided data.
