ADS6123IRHB25 - 12-Bit 80MSPS Low-Power ADC | Texas Instruments
MPN: ADS6123IRHB25 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $36.89 | $36.89 |
| 10 | $34.5 | $345.00 |
| 100 | $30.95 | $3,095.00 |
| 500 | $27.4 | $13,700.00 |
| 1,000 | $23.85 | $23,850.00 |
ADS6123IRHB25 Overview
An analog-to-digital converter (ADC) is an integrated circuit that converts continuous-time analog signals into discrete digital codes for processing by microcontrollers, FPGAs, or DSPs. Pipeline ADCs like the ADS6123 achieve high sample rates (tens to hundreds of MSPS) by distributing conversion work across multiple low-resolution stages, achieving an excellent trade-off between speed, resolution (typically 8-14 bits), and power consumption. The category hierarchy is ADC -> data converter -> data acquisition IC -> signal chain -> mixed-signal semiconductor.
Key specifications of the ADS6123IRHB25 include a 12-bit native resolution, 80 MSPS maximum sampling rate (the IRHB25 suffix selects 80 MSPS within the ADS612x speed grade family), a differential analog input with 2 Vpp full-scale range, and internal reference support. The output interface is software-configurable: DDR LVDS for low-noise high-speed board-level transfer at full 80 MSPS, or parallel CMOS for direct low-cost FPGA connections. Input bandwidth is approximately 500 MHz, and spurious-free dynamic range (SFDR) typically exceeds 75 dBc at 70 MHz input.
Typical applications for the ADS6123IRHB25 include multi-carrier telecom receivers, low-power portable test and measurement instruments, medical imaging front-ends, and baseband processing blocks in wireless infrastructure. The wide analog supply range (3.0 V to 3.6 V) and digital I/O supply range (1.65 V to 3.6 V) ease integration with 3.3 V and 1.8 V FPGA/ASIC logic, removing the need for level translators and reducing BOM cost.
When designing with this ADC, pay close attention to analog input common-mode voltage, clock jitter (below 200 fs RMS is recommended to avoid degrading SNR), and decoupling on the analog supply pins. The exposed thermal pad must be soldered to a sufficient copper pour to maintain junction temperature. Internal reference mode simplifies BOM but external reference mode allows gain calibration across channels.
This page combines distributor pricing, drop-in 80 MSPS/65 MSPS same-family alternatives, and field-ready design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for ADS6123IRHB25 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADS6123IRHB25 (same form factor and footprint) — differing in Analog Supply Voltage, Operating Temperature, Resolution, RoHS Status, Architecture.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADS6123IRHBR
✅ Drop-In✓ In Stock
$9.4 / Unit
View Datasheet →ADS6124IRHB25
✅ Drop-In✓ In Stock
$21.5 / Unit
View Datasheet →ADS6122IRHB25
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
ADS6125IRHB25
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
ADS61B23IRHBT
✅ Drop-In📋 Reference alternative (not in catalog)
ADS6123IRHB25 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bits |
| Sample Rate (max) | 80 MSPS |
| Sample Rate Grade | 80 / 65 MSPS selectable |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Analog Supply Voltage | 3.0 V to 3.6 V |
| Digital Supply Voltage | 1.65 V to 3.6 V |
| Analog Input Type | Differential |
| Full-Scale Input Range | 2 Vpp |
| Output Interface | DDR LVDS or Parallel CMOS (selectable) |
| Integral Linearity Error (EL) | 0.0488 % |
| Power Consumption | 110 mW at 80 MSPS (typical) |
| Operating Temperature | -40 C to +85 C (industrial) |
| Package | 32-VQFN (5x5 mm) PowerPAD |
| Mounting Type | Surface Mount |
| Number of Terminals | 32 |
| MSL Level | 2 (1 year) |
| RoHS Status | Compliant |
ADS6123IRHB25 Pin Configuration
| Pin 1 | AVDD — Analog supply (3.3 V) |
| Pin 2 | AVSS — Analog ground |
| Pin 3 | INP — Differential analog input, positive |
| Pin 4 | INM — Differential analog input, negative |
| Pin 5 | VCM — Common-mode voltage output |
| Pin 6 | REFT — Reference decoupling top |
| Pin 7 | REFB — Reference decoupling bottom |
| Pin 8 | RESET — Reset pin (active low) |
| Pin 9 | CLK — Sample clock input |
| Pin 10 | CLKB — Complementary sample clock input |
| Pin 11 | DRVDD — Digital output driver supply |
| Pin 12 | DRVSS — Digital output driver ground |
| Pin 13 | OVR — Out-of-range indicator |
| Pin 14 | D0 — Data output bit 0 (LSB) |
| Pin 15 | D1 — Data output bit 1 |
| Pin 16 | D2 — Data output bit 2 |
| Pin 17 | D3 — Data output bit 3 |
| Pin 18 | D4 — Data output bit 4 |
| Pin 19 | D5 — Data output bit 5 |
| Pin 20 | D6 — Data output bit 6 |
| Pin 21 | D7 — Data output bit 7 |
| Pin 22 | D8 — Data output bit 8 |
| Pin 23 | D9 — Data output bit 9 |
| Pin 24 | D10 — Data output bit 10 |
| Pin 25 | D11 — Data output bit 11 (MSB) |
| Pin 26 | FCLK — Frame clock output |
| Pin 27 | DCLK — Data clock output |
| Pin 28 | DFS — Digital format select (CMOS/LVDS) |
| Pin 29 | PD — Power-down control |
| Pin 30 | SEN — Serial enable for register access |
| Pin 31 | SDATA — Serial data for register access |
| Pin 32 | SCLK — Serial clock for register access |
Typical Applications
ADS6123IRHB25 is suitable for 7 applications: Wireless Communications Baseband, Portable Test & Measurement Equipment, Medical Imaging Front-Ends, Industrial Process Control and Data Acquisition, Radar and LIDAR Signal Processing, Software Defined Radio (SDR) Receivers, Multi-Carrier Cable and Broadband Headends.
Wireless Communications Baseband
The ADS6123IRHB25's 80 MSPS sample rate and 12-bit resolution make it a good fit for wireless baseband signal chains, particularly in FDD/TDD LTE small cells and 5G sub-6 GHz remote-radio-head (RRH) cards. Designers typically place the ADC between the analog front-end IF stage and the FPGA's digital down-converter (DDC), using DDR LVDS mode to deliver words to the FPGA without overrunning the LVDS receiver lines. Compared with a switching-rail DC-DC supply to the LNA, the ADC's clean digital output can reduce board-level EMI by avoiding extra signal re-drivers.
Recommended
Portable Test & Measurement Equipment
Low power (~110 mW at 80 MSPS) and the small 32-VQFN footprint suit battery-powered oscilloscopes, handheld spectrum analyzers, and field-deployable signal analyzers. The ADS6123IRHB25 supports wide analog-supply flexibility (3.0 V to 3.6 V) and digital I/O down to 1.65 V, allowing direct connection to low-power FPGAs without level translation - critical when total system current budget is below 500 mA. Pin 1 dot-marker orientation simplifies AOI solder inspection on dense, double-sided probe boards.
Recommended
Medical Imaging Front-Ends
Ultrasound, optical coherence tomography (OCT), and confocal laser imaging front-ends require 12-bit dynamic range combined with high channel density. The ADS6123IRHB25 enables many ADCs to time-interleave along a parallel CMOS bus, multiplying effective channel count without changing footprint. Compared with higher-resolution 14-bit parts, the 12-bit result simplifies thermal management across dense probe arrays. Per TI, CMOS output mode supports direct connection to a backplane FPGA multiplexing array.
Recommended
Industrial Process Control and Data Acquisition
Multi-channel industrial DAQ cards in chassis-mount PLCs and vibration-monitoring platforms benefit from the ADS6123IRHB25's industrial -40 C to +85 C temperature range and selectable output interface. Designers can route CMOS data directly to local MCU peripherals or use DDR LVDS for longer backplane traces. The 3.3 V analog supply matches industrial 24 V->3.3 V downstream regulator rails, simplifying overall BOM. Compared with older 1 MSPS ADCs, the 80 MSPS bandwidth supports oversampling for anti-aliasing relaxation.
Recommended
Radar and LIDAR Signal Processing
Automotive and industrial FMCW radar as well as LIDAR digitizer cards need 50 to 100 MSPS sampling with deterministic latency. The ADS6123IRHB25's pipelined architecture exhibits constant-latency sampling propagation, critical for coherent integration across chirps. Its DDR LVDS mode reduces clock-rate-induced jitter on long PCB traces between the ADC and FPGA on stacked-probe assemblies. Per TI applications materials, pin-compatibility with ADS6124/6125/6122 lets designers share PCB layouts across product variants.
Recommended
Software Defined Radio (SDR) Receivers
Wide-bandwidth SDR receivers for amateur, commercial, and military HF/VHF use the ADS6123IRHB25 to sample IF signals directly after the analog downconverter. The 80 MSPS bandwidth covers Nyquist for IFs up to 40 MHz, sufficient for narrow-band amateur segments up to 50 MHz wide. Selectable CMOS output simplifies hookup to Raspberry-Pi-class SBCs with simple GPIO header prototyping. Compared with external audio-Codec ADCs, the 12-bit native architecture provides wider dynamic range without software gain staging.
Recommended
Multi-Carrier Cable and Broadband Headends
Cable TV headend gateways and DOCSIS 3.1 CMTS receiver cards aggregate multiple 50 MHz downstream bands. The ADS6123IRHB25 at 80 MSPS captures 80 MHz total bandwidth including adjacent-channel guard bands, sufficient for an 8x8 capture card scaling to 256 channels. DDR LVDS output signaling also benefits high-noise backplane environments because of low common-mode noise. Per TI reference materials, designers can pair this ADC with a high-speed FPGA on the same ITX-derivative form-factor modules.
Recommended
Recommended Products Summary
Engineering reference data for ADS6123IRHB25 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADS6123IRHBR | ADS6124IRHB25 | ADS6122IRHB25 | ADS6125IRHB25 | ADS61B23IRHBT |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 32-VQFN (5x5) PowerPAD | 32-VQFN (5x5) - same | 32-VQFN (5x5) - same | 32-VQFN (5x5) - same | 32-VQFN (5x5) - same | 32-QFN - same |
| Resolution | 12 bits | 12 bits | 14 bits | 12 bits | 12 bits | 12 bits |
| Maximum Sample Rate | 80 MSPS | 80 MSPS | 80 MSPS | 65 MSPS | 125 MSPS | 80 MSPS |
| Output Interface | DDR LVDS or Parallel CMOS | DDR LVDS or Parallel CMOS | DDR LVDS or Parallel CMOS | DDR LVDS or Parallel CMOS | DDR LVDS or Parallel CMOS | DDR LVDS or Parallel CMOS |
| Analog Supply | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| Power Consumption @ max rate | approx 110 mW | approx 110 mW | approx 130 mW | approx 83 mW | approx 165 mW | approx 145 mW (buffered input) |
| Temperature Grade | Industrial -40 C to +85 C | Industrial -40 C to +85 C | Industrial -40 C to +85 C | Industrial -40 C to +85 C | Industrial -40 C to +85 C | Industrial -40 C to +85 C |
Key Differentiators
- Selectable DDR LVDS or Parallel CMOS output via single pin (vs ADS61B23IRHBT (DDR LVDS only))
- 12-bit/80 MSPS at approximately 110 mW power (vs ADS61B23IRHBT)
- Pin-compatible upgrade/downgrade across ADS612x family (vs ADS6124IRHB25 / ADS6122IRHB25)
Design Notes
Estimated: At 80 MSPS full-rate CMOS output, the ADS6123IRHB25 draws approximately 110 mW from the 3.3 V analog supply. Decouple AVDD directly at each analog pin pair with a 0.1 uF X7R plus a 10 uF bulk ceramic. Per TI, route digital output driver supply DRVDD from a separate ferrite-bead isolated rail to prevent switching noise from coupling back into the analog front-end. A 22 ohm series resistor on DRVDD reduce ringing when the bus drives long PCB traces.
Estimated: The 32-VQFN PowerPAD thermal pad must be soldered to at least 1 square inch of copper pour (4-layer: 1 oz 0.5 W; 6-layer: 1 oz 0.3 W typical). At ~110 mW, junction self-heating under the 32-VQFN (theta_JA roughly 28 C/W on a 1-oz 4-layer board) gives about 3 C rise - well within the 125 C limit. Confirm by thermal camera measurement in your chassis because forced airflow and board stack-up can shift rise significantly.
Keep analog input traces INP/INM length-matched and routed over a continuous ground plane on the upper layer. Avoid placing the ADC across a digital-plane split. For DDR LVDS output mode, route 100 ohm differential pairs on layer-2 over continuous ground with intra-pair skew under 5 ps (about 1 mm). Place a 100 ohm differential termination resistor close to the FPGA receiver. These layout practices per TI minimize spurious content and optimize SFDR near 70 MHz input.
Do not exceed absolute maximum analog input voltage - verify input common-mode stays within 1.5 V of mid-supply. AES-grade jitter below 200 fs RMS is recommended to avoid degrading SNR; an LVPECL or LVDS clock from a low-noise source like the CDCM7005 / LMK04828 family typically achieves this. The RESET pin is active-low; leaving it floating during power-up can put the part into indeterminate states - always drive RESET high via 10 kohm to DRVDD at startup.
Compliance Information
RoHS and REACH compliance from TI product page. Industrial temperature grade -40 C to +85 C. Not AEC-Q100 qualified - choose automotive-qualified Q1 variants for automotive designs.
