ADS6148IRGZ25 - 14-Bit 250 MSPS ADC, DDR LVDS | Texas Instruments
MPN: ADS6148IRGZ25 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $78.5 | $78.50 |
| 10 | $74.2 | $742.00 |
| 100 | $65.8 | $6,580.00 |
| 500 | $58.4 | $29,200.00 |
| 1,000 | $52.1 | $52,100.00 |
ADS6148IRGZ25 Overview
An analog-to-digital converter (ADC) is a semiconductor device that transforms continuous analog signals into discrete digital codes for processing by digital systems. High-speed pipelined ADCs like the ADS6148IRGZ25 are widely used in communications, test and measurement, and imaging systems where signals in the tens to hundreds of MHz must be quantized for digital down-conversion, modulation analysis, or video processing. The device fits within the broader hierarchy of: ADC -> data converter -> signal chain IC -> mixed-signal semiconductor.
Key features include selectable DDR LVDS or parallel CMOS outputs, internal sample-and-hold with 250 MSPS maximum sampling rate, programmable full-scale input range of 1.0 Vpp to 2.0 Vpp, integrated analog input buffer, low-jitter clock input, and a 48-pin QFN package. The DDR LVDS interface doubles per-pin throughput by clocking data on both clock edges, simplifying board routing and reducing the number of FPGA pins needed.
The device is built on TI's proprietary high-speed BiCMOS process, enabling 250 MSPS operation with low aperture jitter and a wide input bandwidth. It is pin-compatible with the ADS5547 family of ADCs, simplifying migration between resolution and sample-rate options within a system platform. Internal references and gain/offset correction simplify the analog front-end design.
Typical applications include multicarrier wireless infrastructure, software-defined radio (SDR), power amplifier linearization, test and measurement instrumentation, high-definition video processing, medical imaging, and radar systems.
When designing with this ADC, attention to the analog input network, PCB layout, and decoupling strategy is critical. Ground the exposed thermal pad to a low-impedance ground plane and route LVDS outputs with controlled 100-ohm differential impedance to preserve signal integrity.
This page synthesizes current distributor pricing, parametric comparisons, pin-compatible alternatives, and practical design notes not consolidated on distributor listings.
Drop-in alternatives for ADS6148IRGZ25 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADS6148IRGZ25 (same form factor and footprint) — differing in Package, Resolution, Analog Supply Voltage, Input Type, Operating Temperature Range.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADS6148IRGZT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
ADS6129IRGZ25
✅ Drop-In✓ In Stock
$23.1 / Unit
View Datasheet →ADS6129IRGZT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
ADS5547IRGZT
✅ Drop-In📋 Reference alternative (not in catalog)
ADS6144IRGZT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
ADS6148IRGZ25 Maximum Ratings & Electrical Characteristics
| Resolution | 14 bits |
| Maximum Sample Rate | 250 MSPS |
| Architecture | Pipelined |
| Number of Input Channels | 1 |
| Output Interface | DDR LVDS / Parallel CMOS (selectable) |
| Analog Input Type | Differential |
| Full-Scale Input Range | 1.0 Vpp to 2.0 Vpp (programmable) |
| Package | 48-VQFN (RGZ) 7x7 mm with exposed thermal pad |
| Package Code | HVQCCN / QFN-48 |
| Pin Count | 48 |
| Terminal Form | No-lead (surface mount) |
| Temperature Grade | Industrial (-40C to +85C) |
| Power Supply | 3.3 V (analog) / 1.8 V or 3.3 V (digital) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Pin Compatibility | Pin-compatible with ADS5547 family |
ADS6148IRGZ25 Pin Configuration
| Pin 1 | AVDD — 3.3 V analog supply |
| Pin 2 | AGND — Analog ground |
| Pin 3 | INP — Differential analog input (positive) |
| Pin 4 | INN — Differential analog input (negative) |
| Pin 5 | VCM — Common-mode voltage reference |
| Pin 6 | VREF — Voltage reference (decouple externally) |
| Pin 7 | REFT — Internal reference top (decouple externally) |
| Pin 8 | REFB — Internal reference bottom (decouple externally) |
| Pin 9 | CLKIN — Differential clock input (positive) |
| Pin 10 | CLKINB — Differential clock input (negative) |
| Pin 11 | DVDD — Digital supply (1.8 V or 3.3 V) |
| Pin 12 | DGND — Digital ground |
| Pin 13 | SDATA — SPI data input |
| Pin 14 | SCLK — SPI clock |
| Pin 15 | SEN — SPI enable (active low) |
| Pin 16 | RESET — Reset (active low) |
| Pin 17 | DRVDD — Output driver supply |
| Pin 18 | DRGND — Output driver ground |
| Pin 19 | D0+/D0 — Data output 0 (LVDS positive or CMOS) |
| Pin 20 | D0- — Data output 0 (LVDS negative) |
| Pin 21 | D1+/D1 — Data output 1 (LVDS positive or CMOS) |
| Pin 22 | D1- — Data output 1 (LVDS negative) |
| Pin 23 | D2+/D2 — Data output 2 (LVDS positive or CMOS) |
| Pin 24 | D2- — Data output 2 (LVDS negative) |
| Pin 25 | D3+/D3 — Data output 3 (LVDS positive or CMOS) |
| Pin 26 | D3- — Data output 3 (LVDS negative) |
| Pin 27 | D4+/D4 — Data output 4 (LVDS positive or CMOS) |
| Pin 28 | D4- — Data output 4 (LVDS negative) |
| Pin 29 | D5+/D5 — Data output 5 (LVDS positive or CMOS) |
| Pin 30 | D5- — Data output 5 (LVDS negative) |
| Pin 31 | D6+/D6 — Data output 6 (LVDS positive or CMOS) |
| Pin 32 | D6- — Data output 6 (LVDS negative) |
| Pin 33 | D7+/D7 — Data output 7 (LVDS positive or CMOS) |
| Pin 34 | D7- — Data output 7 (LVDS negative) |
| Pin 35 | D8+/D8 — Data output 8 (LVDS positive or CMOS) |
| Pin 36 | D8- — Data output 8 (LVDS negative) |
| Pin 37 | D9+/D9 — Data output 9 (LVDS positive or CMOS) |
| Pin 38 | D9- — Data output 9 (LVDS negative) |
| Pin 39 | D10+/D10 — Data output 10 (LVDS positive or CMOS) |
| Pin 40 | D10- — Data output 10 (LVDS negative) |
| Pin 41 | D11+/D11 — Data output 11 (LVDS positive or CMOS) |
| Pin 42 | D11- — Data output 11 (LVDS negative) |
| Pin 43 | D12+/D12 — Data output 12 (LVDS positive or CMOS) |
| Pin 44 | D12- — Data output 12 (LVDS negative) |
| Pin 45 | D13+/D13 — Data output 13 (LVDS positive or CMOS) |
| Pin 46 | D13- — Data output 13 (LVDS negative) |
| Pin 47 | OVR — Out-of-range / over-range flag |
| Pin 48 | NC — No connection |
Typical Applications
ADS6148IRGZ25 is suitable for 6 applications: Multicarrier Wireless Communications Infrastructure, Software-Defined Radio (SDR) Receivers, Power Amplifier Linearization (DPD), Test and Measurement Instrumentation, High Definition Video Imaging Systems, Medical Imaging Equipment.
Multicarrier Wireless Communications Infrastructure
The ADS6148IRGZ25 fits multi-carrier wireless base-station receivers that must digitize wide-bandwidth RF chains for digital down-conversion. Its 250 MSPS sampling rate captures multiple adjacent carriers simultaneously, while the selectable DDR LVDS output streams data into an FPGA at rates up to 250 MHz DDR, reducing pin count relative to parallel CMOS. Pairing the ADC with TI LMX2531 frequency synthesizers and TRF37A75 IF amplifiers preserves SFDR and SNR. The 14-bit resolution maintains dynamic range necessary for ORAN and 4G/5G receiver blades operating under aggressive linearity budgets.
Recommended
Software-Defined Radio (SDR) Receivers
Software-defined radios need a wide-bandwidth front end that hands raw I/Q data to a programmable FPGA or DSP. The ADS6148IRGZ25 provides 14-bit resolution at 250 MSPS, enabling coverage of sub-6 GHz bands after appropriate analog front-end downconversion. Its 48-VQFN footprint shares PCB layout with the ADS5547 family, allowing rapid frequency-band retargeting. Combined with Xilinx Kintex-7 or Intel Cyclone FPGAs, the ADC delivers the throughput needed for FFT-based spectral analysis, signal demodulation, and adaptive filtering. Industrial temperature grade -40C to +85C supports both outdoor and tactical SDR deployments.
Recommended
Power Amplifier Linearization (DPD)
Digital predistortion systems observe PA output through a feedback path and require a wide-bandwidth, high-linearity ADC. The ADS6148IRGZ25's 14-bit resolution captures 3rd- and 5th-order intermodulation distortion with enough accuracy for DPD correction algorithms, while the 250 MSPS rate lets the system observe multi-octave bandwidth PA outputs. The exposed pad QFN package simplifies thermal management in compact remote-radio-head designs. Place the ADC downstream of a TRF371125 IQ demodulator to recover baseband envelopes for the DSP LUT update loop.
Recommended
Test and Measurement Instrumentation
In oscilloscopes, spectrum analyzers, and digitizers the ADS6148IRGZ25 serves as a high-speed capture ADC. Its DDR LVDS output can feed FPGA-based time-interleave channels or ASIC post-processors at 500 Mbps per pair. Engineers targeting a 1 Gs/s aggregate often synchronize four ADS6148 devices with calibrated clock skew. The industrial temperature grade supports both lab and field-deployed instruments. The same board can be reused by swapping to ADS6129 when 12-bit precision is acceptable in lower-cost variants of the instrument.
Recommended
High Definition Video Imaging Systems
Pro HD video digitizers rely on the ADS6148IRGZ25 to convert component analog video (YPbPr) and SDI streams into 14-bit digital samples suitable for scaling, deinterlacing, and color correction pipelines. At 250 MSPS the ADC supports 1080p and 4K capture workflows with adequate oversampling. The 48-pin QFN footprint fits inside dense mezzanine boards used in broadcast and medical video infrastructure. Combined with an FPGA-based scaler the system outputs HDMI 2.0 or 12G-SDI streams with low artifact content.
Recommended
Medical Imaging Equipment
Ultrasound and PET imaging systems require high-resolution digitizers that can sample multiple channels simultaneously. The ADS6148IRGZ25, in a multi-board array configuration, captures RF signals from ultrasound transducers with 14-bit accuracy at 250 MSPS to enable harmonic imaging and Doppler flow analysis. Its 48-VQFN (RGZ) footprint enables dense PCB layouts in portable cart-based ultrasound systems. The exposed thermal pad simplifies heat extraction in continuous-duty clinical use. The -40C to +85C industrial operating range supports ventilator-adjacent imaging carts.
Recommended
Recommended Products Summary
Engineering reference data for ADS6148IRGZ25 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADS6148IRGZT | ADS6129IRGZ25 | ADS6129IRGZT | ADS5547IRGZT | ADS6144IRGZT |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same |
| Resolution | 14 bits | 14 bits | 12 bits | 12 bits | 14 bits | 14 bits |
| Maximum Sample Rate | 250 MSPS | 250 MSPS | 250 MSPS | 250 MSPS | 105 MSPS | 105 MSPS |
| Output Interface | DDR LVDS / Parallel CMOS | DDR LVDS / Parallel CMOS | DDR LVDS / Parallel CMOS | DDR LVDS / Parallel CMOS | DDR LVDS / Parallel CMOS | DDR LVDS / Parallel CMOS |
| Number of Input Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Temperature Grade | Industrial (-40C to +85C) | Industrial | Industrial | Industrial | Industrial | Industrial |
| Approximate 1-Unit Price | $78.50 | $78.50 (same die) | $70.00 (approx) | $70.00 (approx) | $62.00 (approx) | $58.00 (approx) |
Key Differentiators
- Pin-compatible 48-VQFN family for fast resolution/sample-rate scaling (vs ADS5547 family)
- 250 MSPS at 14-bit resolution (vs ADS6129IRGZ25)
- DDR LVDS output mode for reduced FPGA pin count (vs ADS6144IRGZT)
Design Notes
The ADS6148IRGZ25 in 48-VQFN (RGZ) requires a low-impedance ground connection via the exposed thermal pad. Solder the pad to a continuous ground plane with thermal via stitching arrays (typically 4-9 vias on 1 mm pitch) directly beneath the package. Without this connection, the device will be both electrically degraded (ground bounce coupling into the analog input) and thermally insufficient. The 48-VQFN's 7x7 mm footprint requires keep-out zones around the body for trace routing; place decoupling capacitors as close as possible to power pins.
DDR LVDS outputs of the ADS6148IRGZ25 must be length-matched within each pair and across pairs to maintain setup/hold margin at the receiving FPGA. Use 100-ohm differential controlled-impedance routing with continuous reference plane on an adjacent ground layer. Apply AC-coupling at the receiver for common-mode isolation. At 250 MSPS the toggling edge is in the 4 ns range; ensure the FPGA capture register clocks the DDR center-aligned with a delay-tuned clock tree.
Estimated: When decoding the analog front-end below the ADC input full-scale, ensure the common-mode voltage (VCM) pin is decoupled with 0.1 uF ceramic to ground. Missing the VCM bypass results in degraded linearity and may cause the input buffer to oscillate. Maintain a single ground reference from the analog input connector to the ADC ground pin. Most customer-returned ADC boards fail due to insufficient input network bandwidth — ensure the transformer secondary is damped with the proper termination resistor across the ADC inputs.
Compliance Information
RoHS compliant and lead-free per TI product page. AEC-Q100 qualification not applicable (industrial temperature grade only).
