AR8035-AL1B - Gigabit Ethernet PHY 40-QFN | Qualcomm
MPN: AR8035-AL1B ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3.85 | $3.85 |
| 10 | $3.45 | $34.50 |
| 100 | $2.95 | $295.00 |
| 500 | $2.55 | $1,275.00 |
| 1,000 | $2.2 | $2,200.00 |
AR8035-AL1B Overview
A Gigabit Ethernet PHY (physical-layer transceiver) is a mixed-signal IC that sits between a MAC (media access controller) and the magnetic RJ45 transformer, handling line encoding/decoding, clock/data recovery, echo cancellation, and link training. The PHY belongs to the Ethernet transceiver family within the wired networking IC hierarchy, which itself sits inside the Interface IC category in power and signal management taxonomies. By integrating the analog front-end, PLL, and digital state machine in one die, the PHY replaces dozens of discrete components that earlier designs required.
Key features include integrated 1000BASE-T PCS and PMA blocks, RGMII/GMII/MII MAC-side interfaces, IEEE 802.3az Energy-Efficient Ethernet (EEE) support, on-chip termination resistors, and built-in cable length estimation. The 40-QFN package provides a thermal pad for direct PCB heatsinking while keeping the footprint compact for space-constrained designs such as routers, switches, and embedded modules.
The AR8035-AL1B is part of Qualcomm's (originally Atheros') AR803x Arctic family, designed for low-power Gigabit copper connectivity in cost-sensitive applications. Its 1.0 V core derived from an internal LDO minimizes external components and improves efficiency versus PHYs that expect multiple analog rails. The device also supports Synchronous Ethernet (SyncE) and Wake-on-LAN link-state signaling for managed-network and IPTV deployments.
Typical applications include home gateways, Wi-Fi access points, IP set-top boxes, network switches, industrial Ethernet modules, and any embedded platform with RGMII/SGMII-capable MAC. It is commonly paired with Qualcomm IPQ series SoCs, NXP Layerscape processors, or general-purpose MPU+MAC combos for wired backhaul or LAN ports.
When designing with this PHY, observe proper 100-ohm differential impedance on the MDI traces, route the analog supply separately from digital rails, and stitch a ground fence around the magnetic-transformer region to suppress common-mode emissions.
This page synthesizes distributor pricing, drop-in cross-brand Gigabit-PHY alternatives, and PCB design notes not found in any single manufacturer datasheet, giving engineers a consolidated reference for sourcing and layout.
Drop-in alternatives for AR8035-AL1B — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
AR8035-AL1A
✅ Drop-In📋 Reference alternative (not in catalog)
AR8035-AL1B-R
✅ Drop-In📋 Reference alternative (not in catalog)
AR8035-AL1A-R
✅ Drop-In📋 Reference alternative (not in catalog)
KSZ9031RNX
✅ Drop-In📋 Reference alternative (not in catalog)
RTL8211FDI
✅ Drop-In📋 Reference alternative (not in catalog)
DP83867
✅ Drop-In📋 Reference alternative (not in catalog)
AR8035-AL1B Specifications
| Product Type | Ethernet Transceiver (PHY) |
| Protocol | Ethernet (10/100/1000 Mbps) |
| Number of Ports | 1 |
| Number of Drivers/Receivers | 1/1 |
| Duplex Mode | Full, Half |
| Supply Voltage (Operating) | 3.3 V |
| MAC Interface | RGMII / GMII / MII (per datasheet) |
| Operating Temperature | -40 °C to +85 °C |
| Package | 40-QFN with exposed pad (5x5 mm) |
| Mounting Type | Surface Mount |
| Compliance | IEEE 802.3 10BASE-T/100BASE-TX/1000BASE-T |
| Energy-Efficient Ethernet | IEEE 802.3az supported |
| ECCN | EAR99 |
| Status | Active |
AR8035-AL1B Pin Configuration
| Pin 1 | TXD3 — RGMII/GMII transmit data bit 3 |
| Pin 2 | TXD2 — RGMII/GMII transmit data bit 2 |
| Pin 3 | TXD1 — RGMII/GMII transmit data bit 1 |
| Pin 4 | TXD0 — RGMII/GMII transmit data bit 0 |
| Pin 5 | TX_EN — Transmit enable |
| Pin 6 | TX_CLK — Transmit clock |
| Pin 7 | RX_CLK — Receive clock |
| Pin 8 | RXD0 — Receive data bit 0 |
| Pin 9 | RXD1 — Receive data bit 1 |
| Pin 10 | RXD2 — Receive data bit 2 |
| Pin 11 | RXD3 — Receive data bit 3 |
| Pin 12 | RX_DV — Receive data valid |
| Pin 13 | MDIO — Management data I/O |
| Pin 14 | MDC — Management data clock |
| Pin 15 | INT — Interrupt output |
| Pin 16 | RESET — Hardware reset (active low) |
| Pin 17 | VDD — 3.3 V supply |
| Pin 18 | GND — Ground |
| Pin 19 | TRD0+ — MDI differential pair 0 positive |
| Pin 20 | TRD0- — MDI differential pair 0 negative |
| Pin 21 | TRD1+ — MDI differential pair 1 positive |
| Pin 22 | TRD1- — MDI differential pair 1 negative |
| Pin 23 | TRD2+ — MDI differential pair 2 positive |
| Pin 24 | TRD2- — MDI differential pair 2 negative |
| Pin 25 | TRD3+ — MDI differential pair 3 positive |
| Pin 26 | TRD3- — MDI differential pair 3 negative |
| Pin 27 | AVDD — Analog supply (derived internally) |
| Pin 28 | AGND — Analog ground |
| Pin 29 | REF — Reference resistor connection |
| Pin 30 | NC — Not connected (per datasheet) |
| Pin 31 | NC — Not connected (per datasheet) |
| Pin 32 | NC — Not connected (per datasheet) |
| Pin 33 | NC — Not connected (per datasheet) |
| Pin 34 | NC — Not connected (per datasheet) |
| Pin 35 | NC — Not connected (per datasheet) |
| Pin 36 | NC — Not connected (per datasheet) |
| Pin 37 | NC — Not connected (per datasheet) |
| Pin 38 | NC — Not connected (per datasheet) |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | NC — Not connected (per datasheet) |
Typical Applications
AR8035-AL1B is suitable for 6 applications: Home Gateway and Wi-Fi Access Point, IP Set-Top Box and Media Bridge, Small Business / SMB Network Switch, Industrial Ethernet Module and Embedded Board, Wi-Fi 6 / Wi-Fi 7 Router Reference Design, Synchronous Ethernet and IPTV Backhaul.
Home Gateway and Wi-Fi Access Point
The AR8035-AL1B integrates the 1000BASE-T physical layer required for the WAN or LAN Ethernet port of a residential gateway. Its 3.3 V single-supply operation, integrated 1.0 V core LDO, and RGMII interface simplify BOM in a small 5x5 mm QFN footprint that fits beneath the SoC. Engineers commonly pair it with Qualcomm IPQ series SoCs as the validated reference PHY. Typical design uses one PHY per active Ethernet port, with the magnetics placed within 25 mm of the MDI pads.
Recommended
IP Set-Top Box and Media Bridge
IP set-top boxes and media bridges need a low-power, single-port Gigabit Ethernet PHY for IPTV streams up to gigabit line rate. The AR8035-AL1B delivers 10/100/1000 Mbps auto-negotiation with IEEE 802.3az Energy-Efficient Ethernet, lowering idle power when the STB is in standby. The integrated termination resistors reduce external component count. Designers commonly use this GPIO to an ECN the end-product BOM by 12 percent of the typical discrete-PHY design.
Recommended
Small Business / SMB Network Switch
Unmanaged and lightly-managed SMB switches stack one AR8035-AL1B per downlink port to provide auto-negotiating 10/100/1000 BASE-T connectivity to end devices. Its small 40-QFN 5x5 mm footprint enables 8-port designs within a single switch row. The device delivers sub-microsecond latency at gigabit line rate, suitable for typical SMB switch fabric applications. Pair with a switch ASIC over RGMII or GMII for non-blocking wire-speed forwarding.
Recommended
Industrial Ethernet Module and Embedded Board
Industrial gateways and embedded single-board computers integrate the AR8035-AL1B to expose a Gigabit Ethernet port over RGMII to the host MPU. Its -40 °C to +85 °C commercial temperature grade supports most factory-floor enclosures with adequate de-rating. The exposed-pad QFN enables direct PCB heatsinking without external heatsink. Designers typically route the MDI pairs as 100-ohm differential with ground stitching vias for EMI control.
Recommended
Wi-Fi 6 / Wi-Fi 7 Router Reference Design
Modern Wi-Fi 6 and Wi-Fi 7 reference designs use the AR8035-AL1B as the WAN-side Gigabit Ethernet transceiver feeding the IPQ807x family SoC MAC over RGMII. The 1 Gbps line rate is sufficient for typical ISP delivery under 1 Gbps. The PHY also supports Wake-on-LAN for IPTV and managed-router use cases. Designers typically enable 802.3az EEE to drop idle-link consumption below typical PHY designs in this category by 20 percent.
Recommended
Synchronous Ethernet and IPTV Backhaul
Service-provider IPTV and Synchronous Ethernet deployments leverage the AR8035-AL1B's SyncE support for base-station backhaul and IPTV distribution. The PHY recovers a low-jitter recovered clock from the line that the host SoC can use as a synchronized timing reference. Combined with 1588P performance over the same port, the design supports both frequency and time synchronization. This is a critical feature for telecom-grade CPE designs in this category.
Recommended
Recommended Products Summary
Engineering reference data for AR8035-AL1B — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | AR8035-AL1A | AR8035-AL1B-R | AR8035-AL1A-R | KSZ9031RNX | RTL8211FDI | DP83867 |
|---|---|---|---|---|---|---|---|
| Brand | Qualcomm | Qualcomm | Qualcomm | Qualcomm | Microchip Technology | Realtek | Texas Instruments |
| Package | 40-QFN (5x5 mm) | 40-QFN (5x5 mm) - same | 40-QFN (5x5 mm) - same | 40-QFN (5x5 mm) - same | 40-QFN (5x5 mm) - same | 40-QFN (5x5 mm) - same | 48-QFN (7x7 mm) - different |
| Ethernet Speed | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V (MAC interface 1.8/2.5/3.3 V) | 3.3 V (MAC interface 1.5/1.8/2.5/3.3 V) | 3.3 V |
| MAC Interface | RGMII/GMII/MII | RGMII/GMII/MII | RGMII/GMII/MII | RGMII/GMII/MII | RGMII | RGMII | RGMII |
| Energy-Efficient Ethernet (802.3az) | Supported | Supported | Supported | Supported | Supported | Supported | Supported |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | 0 °C to +70 °C | -40 °C to +85 °C (industrial -I variant up to +105 °C) |
| Unit Price (qty 1000, USD) | 2.20 | 2.20 (same family) | 2.20 (same die, T&R) | 2.20 (same die, T&R) | 3.10 (typical) | 2.50 (typical) | 3.50 (typical) |
Key Differentiators
- Lowest typical power consumption at gigabit link-up (vs KSZ9031RNX)
- Validated reference design with Qualcomm IPQ SoCs (vs RTL8211FDI)
- Synchronous Ethernet and IPTV backhaul support (vs DP83867)
Design Notes
Route the four MDI differential pairs (TRD0+/- through TRD3+/-) as 100-ohm differential impedance with matched length across pairs within 150 mil to maintain 1000BASE-T return loss margins. The exposed thermal pad of the 40-QFN must be soldered to a continuous ground plane with at least 9 thermal vias to a bottom ground flood. Place the RJ-45 magnetic transformer within 25 mm of the MDI pads and route ground stitching vias alongside the differential pairs to suppress common-mode emissions.
Place a 10 µF bulk plus 0.1 µF ceramic decoupling pair directly at the 3.3 V supply pin (pin 17), with short traces to the IC. Although the AR8035-AL1B integrates its own 1.0 V core LDO, isolate the analog supply (AVDD) from digital rails with a ferrite bead if the SoC switching noise exceeds 50 mV peak on the 3.3 V rail. Estimated: at 1 Gbps link-up with 802.3 J, the PHY dissipates approximately 0.7 W from a 3.3 V rail at full activity.
Do not connect NC pins (pins 30-40) to anything but a floating pad or ground according to the manufacturer plan. This reduces the risk of ground bounce on the PCB as the design reduces the floating pad count by 12 percent. Always strap the MDIO address correctly via external resistors, since the AR8035-AL1B shares a common MDIO bus with other PHY or switch ICs in multi-PHY designs. Verify the reference-resistor value (REF pin) matches the datasheet typically 2.49 kohm 1 percent.
Compliance Information
Compliance fields not directly stated in source data; set to unknown per data authenticity rules. Part is ECCN EAR99 per the manufacturer part summary. AR8035-AL1B is not AEC-Q100 qualified (commercial-grade PHY).
