ATMEGA128-16AN - 8-Bit AVR MCU 128KB 16MHz TQFP-64 | Microchip
MPN: ATMEGA128-16AN β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.4 | $12.40 |
| 10 | $11.16 | $111.60 |
| 100 | $9.92 | $992.00 |
| 500 | $8.68 | $4,340.00 |
| 1,000 | $7.44 | $7,440.00 |
ATMEGA128-16AN Overview
An 8-bit AVR microcontroller is a single-chip processor built on the AVR enhanced RISC architecture, in which most of the 131 instructions execute in a single clock cycle. Within the system hierarchy, the microcontroller sits between simple logic ICs and application processors, integrating CPU, program memory, data memory, timers, and communication peripherals into one device for embedded control tasks.
Key features include 53 general-purpose I/O lines, 32 general-purpose working registers, four flexible timers/counters with compare modes and PWM, and an 8-channel 10-bit A/D converter. Dual USARTs, a byte-oriented Two-Wire Interface (I2C-compatible), and a hardware SPI port provide multi-protocol connectivity for sensors, displays, and industrial networks.
Technically, the fully static core sustains performance from DC to 16 MHz, while the Read-While-Write FLASH allows code updates during operation. An RTC with separate oscillator, JTAG boundary-scan, and an ATmega103 compatibility mode (via the M103C fuse) simplify legacy design migration. This version is rated at 16 MHz at 4.5-5.5V with a -40C to +85C industrial temperature rating.
Typical applications include industrial automation control panels, HVAC and building-management systems, battery-monitoring instrumentation, and motor-control nodes using the PWM channels.
Design consideration: for lowest power consumption in idle and power-down modes, configure unused I/O pins as inputs with internal pull-ups and use the power-reduction registers to clock-gate unused peripherals.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for ATMEGA128-16AN β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ATMEGA128-16AN (same form factor and footprint) β differing in Instructions, ADC, Communication Interfaces, Core Architecture, Flash Memory.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
ATMEGA128-16AU
β Drop-Inβ In Stock
$14.3 / Unit
View Datasheet βATMEGA128-16AUR
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
ATMEGA128-16AI
β Drop-Inβ In Stock
$5.9 / Unit
View Datasheet βATMEGA64-16AU
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
AT90CAN128-16AU
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
ATMEGA1281-16AU
β Drop-Inπ Reference alternative (not in catalog)
ATMEGA128-16AN Maximum Ratings & Electrical Characteristics
| Core Architecture | 8-bit AVR RISC |
| Core Size | 8-bit |
| Max Clock Frequency | 16 MHz |
| Peak Throughput | 16 MIPS at 16 MHz |
| Flash Memory | 128 KB (64K x 16) |
| SRAM | 4 KB |
| EEPROM | 4 KB |
| Operating Voltage Range | 4.5 V to 5.5 V |
| General Purpose I/O | 53 lines |
| Timers/Counters | 4 with compare modes and PWM |
| ADC | 8-channel, 10-bit |
| USART | 2 |
| Communication Interfaces | 2x USART, TWI (I2C), SPI |
| Debug / Boundary Scan | JTAG (IEEE 1149.1 interface for on-chip debugging) |
| Instructions | 131 instructions, most single-cycle |
| Package | 64-TQFP (14x14 mm) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +85C |
| Working Registers | 32 general purpose |
| RoHS Status | unknown |
ATMEGA128-16AN Pin Configuration
| Pin 1 | PEN β Programming enable for external programming mode |
| Pin 2 | PE0 (RXD0) β I/O / USART0 receive |
| Pin 3 | PE1 (TXD0) β I/O / USART0 transmit |
| Pin 4 | PE2 (XCK0/AIN0) β I/O / USART0 clock / analog comparator input |
| Pin 5 | PE3 (OC3A/AIN1) β I/O / Timer3 output compare A / comparator input |
| Pin 6 | PE4 (OC3B/INT4) β I/O / Timer3 output compare B / external interrupt 4 |
| Pin 7 | PE5 (OC3C/INT5) β I/O / Timer3 output compare C / external interrupt 5 |
| Pin 8 | PE6 (T3/INT6) β I/O / Timer3 clock input / external interrupt 6 |
| Pin 9 | PE7 (ICP3/INT7) β I/O / Timer3 input capture / external interrupt 7 |
| Pin 10 | GND β Ground |
| Pin 11 | VCC β Digital supply voltage |
| Pin 12 | PB0 (SS) β I/O / SPI slave select |
| Pin 13 | PB1 (SCK) β I/O / SPI clock |
| Pin 14 | PB2 (MOSI) β I/O / SPI master data out |
| Pin 15 | PB3 (MISO) β I/O / SPI master data in |
| Pin 16 | PB4 (OC0) β I/O / Timer0 output compare / PWM |
| Pin 17 | PB5 (OC1A) β I/O / Timer1 output compare A / PWM |
| Pin 18 | PB6 (OC1B) β I/O / Timer1 output compare B / PWM |
| Pin 19 | PB7 (OC2/OC1C) β I/O / Timer2 output compare / Timer1 output compare C |
| Pin 20 | PG3 (TOSC2) β I/O / RTC oscillator output |
| Pin 21 | PG4 (TOSC1) β I/O / RTC oscillator input |
| Pin 22 | RESET β Active-low reset input |
| Pin 23 | VCC β Digital supply voltage |
| Pin 24 | GND β Ground |
| Pin 25 | XTAL2 β Main oscillator output |
| Pin 26 | XTAL1 β Main oscillator input / external clock |
| Pin 27 | PD0 (SCL/INT0) β I/O / TWI clock / external interrupt 0 |
| Pin 28 | PD1 (SDA/INT1) β I/O / TWI data / external interrupt 1 |
| Pin 29 | PD2 (TXD1/INT2) β I/O / USART1 transmit / external interrupt 2 |
| Pin 30 | PD3 (RXD1/INT3) β I/O / USART1 receive / external interrupt 3 |
| Pin 31 | PD4 (ICP1) β I/O / Timer1 input capture |
| Pin 32 | PD5 (XCK1) β I/O / USART1 clock |
| Pin 33 | PD6 (T1) β I/O / Timer1 external clock |
| Pin 34 | PD7 (T0) β I/O / Timer0 external clock |
| Pin 35 | PG0 (WR) β I/O / external memory write strobe |
| Pin 36 | PG1 (RD) β I/O / external memory read strobe |
| Pin 37 | PC0 (A8) β I/O / external memory address line 8 |
| Pin 38 | PC1 (A9) β I/O / external memory address line 9 |
| Pin 39 | PC2 (A10) β I/O / external memory address line 10 |
| Pin 40 | PC3 (A11) β I/O / external memory address line 11 |
| Pin 41 | PC4 (A12) β I/O / external memory address line 12 |
| Pin 42 | PC5 (A13) β I/O / external memory address line 13 |
| Pin 43 | PC6 (A14) β I/O / external memory address line 14 |
| Pin 44 | PC7 (A15) β I/O / external memory address line 15 |
| Pin 45 | GND β Ground |
| Pin 46 | AVCC β ADC and Port A supply voltage |
| Pin 47 | PA0 (AD0) β I/O / ADC input 0 / external memory address/data line 0 |
| Pin 48 | PA1 (AD1) β I/O / ADC input 1 / external memory address/data line 1 |
| Pin 49 | PA2 (AD2) β I/O / ADC input 2 / external memory address/data line 2 |
| Pin 50 | PA3 (AD3) β I/O / ADC input 3 / external memory address/data line 3 |
| Pin 51 | PA4 (AD4) β I/O / ADC input 4 / external memory address/data line 4 |
| Pin 52 | PA5 (AD5) β I/O / ADC input 5 / external memory address/data line 5 |
| Pin 53 | PA6 (AD6) β I/O / ADC input 6 / external memory address/data line 6 |
| Pin 54 | PA7 (AD7) β I/O / ADC input 7 / external memory address/data line 7 |
| Pin 55 | PF0 (ADC0) β I/O / ADC input 0 |
| Pin 56 | PF1 (ADC1) β I/O / ADC input 1 |
| Pin 57 | PF2 (ADC2) β I/O / ADC input 2 |
| Pin 58 | PF3 (ADC3) β I/O / ADC input 3 |
| Pin 59 | PF4 (ADC4/TCK) β I/O / ADC input 4 / JTAG test clock |
| Pin 60 | PF5 (ADC5/TMS) β I/O / ADC input 5 / JTAG test mode select |
| Pin 61 | PF6 (ADC6/TDO) β I/O / ADC input 6 / JTAG test data out |
| Pin 62 | PF7 (ADC7/TDI) β I/O / ADC input 7 / JTAG test data in |
| Pin 63 | AREF β ADC reference voltage |
| Pin 64 | GND β Ground |
Typical Applications
ATMEGA128-16AN is suitable for 6 applications: Industrial Automation Control, HVAC and Building Management Systems, Motor Control Nodes, Instrumentation and Data Loggers, Embedded Networking Gateways, ATmega103 Legacy Board Migration.
Industrial Automation Control
The ATMEGA128-16AN fits industrial automation nodes because its -40C to +85C rating, 53 GPIO lines, and 4.5-5.5V supply tolerance map directly onto 5V industrial backplanes. Four timers with compare modes and PWM drive motor or heater control, while dual USARTs implement Modbus RTU and service links in parallel. The 128 KB flash leaves headroom for protocol stacks, state machines, and HMI logic, and JTAG boundary scan supports production board test. Placing the MCU between RS-485 transceivers and optocoupled I/O gives a deterministic single-cycle-execution core with 16 MIPS throughput; unlike 3V-only successors, no level shifting is needed on legacy 5V sensor buses.
Recommended
HVAC and Building Management Systems
In HVAC controllers, the ATMEGA128-16AN's 8-channel 10-bit ADC samples temperature, humidity, and pressure sensors across multiple zones, while the RTC with a separate 32.768 kHz oscillator (TOSC1/TOSC2 on PG3/PG4) maintains schedules through power interruptions. The 4 KB EEPROM stores calibration constants and setpoints without flash wear. TWI (I2C) addresses digital sensors and display drivers, and the 128 KB flash accommodates BACnet-like protocol handling. Its 5V operation simplifies interfacing with legacy damper-actuator and relay-drive circuits. Power-down mode with watchdog wake-up reduces standby consumption in battery-backed thermostat variants, and the M103C compatibility mode eases upgrades of older ATmega103-based controller boards.
Recommended
Motor Control Nodes
The ATMEGA128-16AN suits motor-control supervision with four flexible timers providing complementary PWM and compare channels; PB5-PB7 deliver OC1A/OC1B/OC1C outputs suitable for driving H-bridge gate-driver logic at 16 MHz timer resolution. The 10-bit ADC reads back shunt currents and bus voltage with up to 8 channels, enabling closed-loop speed regulation in firmware. Dual USARTs separate fieldbus commands from diagnostic telemetry. The 16 MIPS RISC core executes PI control loops deterministically without pipeline jitter. Designers should pair the PWM outputs with opto-isolated gate drivers and use the JTAG interface for in-target tuning of control parameters during commissioning.
Recommended
Instrumentation and Data Loggers
For battery-monitoring and field instrumentation, the ATMEGA128-16AN combines an 8-channel 10-bit ADC with 4 KB SRAM buffering and a 4 KB EEPROM for nonvolatile logging, making standalone acquisition nodes feasible without external memory. SPI and TWI interfaces extend capacity with serial FLASH or FRAM when needed, and the 128 KB flash hosts floating-point conversion and calibration code with room to spare. Read-While-Write flash supports field firmware updates over the diagnostic USART. Its fully static core permits clocking down for precision, low-noise measurements, then returning to 16 MHz for communication bursts, balancing accuracy and responsiveness in portable instruments.
Recommended
Embedded Networking Gateways
The ATMEGA128-16AN works as a protocol-conversion gateway between serial field devices and Ethernet or CAN backbones. Two independent hardware USARTs (PE0/PE1 and PD2/PD3 with XCK1 on PD5) sustain simultaneous links, while the byte-oriented Two-Wire Interface and hardware SPI connect auxiliary controllers. The 128 KB flash accommodates dual protocol stacks plus buffering logic, and the RAMPZ-capable memory model is supported transparently by C compilers such as CodeVisionAVR. Because the device is 100% pin compatible with ATmega103, gateway vendors can refresh legacy ATmega103 hardware without PCB redesign. JTAG on-chip debugging accelerates stack integration and fault tracing during development.
Recommended
ATmega103 Legacy Board Migration
The manufacturer datasheet states the ATmega128 is 100% pin compatible with ATmega103 and can replace it on current printed circuit boards, making the ATMEGA128-16AN the canonical modernization path for obsolete ATmega103 designs. Program the M103C fuse to emulate ATmega103 RAM, I/O pin, and interrupt-vector behavior, or run in native mode to unlock 53 I/O lines, TWI, and more timers while reusing the identical TQFP-64 footprint. Microchip's application note "Replacing ATmega103 by ATmega128" lists the memory-map and fuse considerations. The 16 MHz speed grade doubles the legacy part's throughput on the same 5V board, typically eliminating timing-margin issues in refreshed production runs.
Recommended
Recommended Products Summary
Engineering reference data for ATMEGA128-16AN β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ATMEGA128-16AU | ATMEGA128-16AI | ATMEGA64-16AU | AT90CAN128-16AU | ATMEGA1281-16AU |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 64-TQFP (14x14 mm) | 64-TQFP (14x14 mm) - same | 64-TQFP (14x14 mm) - same | 64-TQFP (14x14 mm) - same | 64-TQFP (14x14 mm) - same | 64-TQFP (14x14 mm) - same |
| Flash Memory | 128 KB | 128 KB | 128 KB | 64 KB | 128 KB | 128 KB |
| SRAM | 4 KB | 4 KB | 4 KB | 2 KB | 4 KB | 8 KB |
| Max Clock / Throughput | 16 MHz / 16 MIPS | 16 MHz / 16 MIPS | 16 MHz / 16 MIPS | 16 MHz / 16 MIPS | 16 MHz / 16 MIPS | 16 MHz / 16 MIPS |
| Supply Voltage | 4.5 V - 5.5 V | 4.5 V - 5.5 V | 4.5 V - 5.5 V | 4.5 V - 5.5 V | 4.5 V - 5.5 V | 2.7 V - 5.5 V (16 MHz needs 4.5 V) |
| Special Peripherals | TWI, SPI, 2 USART, 10-bit ADC, JTAG | Same as this product | Same as this product | TWI, SPI, USART, 10-bit ADC, JTAG | Adds CAN 2.0B controller | Updated peripheral set, mega1280-family pinout |
| Pin Compatibility with ATmega128 | Reference | 100% (same die) | 100% (same die) | Largely compatible pin family | Pin-compatible footprint, peripheral allocation differs | Not pin-identical (different family pinout) |
| Key Differentiation | Classic ATmega128, 5V industrial grade | Alternate packaging/compliance suffix | Industrial temperature suffix option | Cost-down with half the memory | Native CAN bus for vehicle/industrial networks | Successor family for new designs |
Key Differentiators
- ATmega103 legacy migration without PCB change (vs ATMEGA1281-16AU)
- Full 16 MHz speed at 5V industrial temperature (vs ATMEGA64-16AU)
- Deterministic single-cycle RISC with JTAG (vs AT90CAN128-16AU)
Design Notes
The ATMEGA128-16AN in TQFP-64 requires a decoupling capacitor (100 nF ceramic) at each VCC/AVCC pin pair (pins 11/23 VCC, 46 AVCC) placed within 5 mm of the pin, with a solid ground return to pins 10, 24, 45, and 64. Route the 16 MHz crystal close to XTAL1/XTAL2 (pins 26/25) with short, symmetrical traces and keep the RTC crystal on PG3/PG4 isolated from switching traces. Use AVCC with an LC filter (10 uH + 100 nF) when ADC accuracy matters, and tie AREF to a clean reference through the recommended capacitor network.
Three classic ATmega128 pitfalls: (1) PF4-PF7 default to JTAG function after reset - if you need them as ADC inputs or GPIO, clear the JTAGEN fuse or set the JTD bit in software twice in succession; (2) the M103C fuse ships in ATmega103 compatibility mode on some programming tools, silently masking extra SRAM, I/O, and interrupt vectors - disable it for native operation unless migrating ATmega103 boards; (3) pin 1 is PEN (programming enable), not a general-purpose pin - do not drive it high unintentionally during reset or the device may enter programming mode.
Estimated: at 16 MHz and 5V, the ATmega128 active supply current is typically on the order of 20-25 mA per manufacturer datasheet curves (verify against the current datasheet revision for your lot), so design the 5V rail with at least 50 mA margin for the MCU plus I/O loads. Use power-reduction registers (PRR) to clock-gate unused peripherals such as Timer2 and ADC in idle periods, and select power-down mode (microamp-class current) for battery-backed standby. Brown-out detection should be enabled at approximately 4.0-4.2V via the BODLEVEL fuses to prevent EEPROM corruption during 5V rail droop.
When using the external-memory interface (PG0/PG1 WR/RD strobes with PA0-PA7 multiplexed address/data), keep bus traces under 10 cm and add series termination (22-33 ohm) on the strobe lines to limit ringing at 16 MHz. SPI lines on PB0-PB3 to off-board peripherals should use short traces with a ground return; if driving long cables, buffer SCK and MOSI. For the dual USARTs running at 115200 baud, verify the baud-rate generator error from the datasheet UBRR tables at 16 MHz - 115200 baud gives a small but acceptable error, while nonstandard rates may require clock adjustment.
Compliance Information
RoHS/REACH/lead-free status not stated in the captured distributor data; verify on the official Microchip product page or the distributor material declaration before procurement.
