ATSAMA5D35A-CU - ARM Cortex-A5 MPU 536MHz LFBGA-324 | Microchip
MPN: ATSAMA5D35A-CU ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $26.4 | $264.00 |
| 100 | $24.1 | $2,410.00 |
| 500 | $22.85 | $11,425.00 |
| 1,000 | $21.4 | $21,400.00 |
ATSAMA5D35A-CU Overview
An ARM Cortex-A5 MPU is a 32-bit application-class microprocessor core based on the ARMv7-A architecture, designed for mainstream embedded Linux and real-time operating system workloads. The Cortex-A5 features the ARM NEON SIMD engine (optional in this variant), single-precision and double-precision VFPv4 floating-point hardware, and supports symmetric multiprocessing. Within the broader taxonomy, the MPU sits above microcontrollers in compute capability while remaining below application processors that integrate GPUs or display controllers; it is a central building block of power-managed industrial and IoT edge nodes.
Key features include an integrated LCD TFT controller supporting up to 2048x2048 resolution, dual Ethernet GMAC (10/100/1000 Mbps) with IEEE 1588 hardware timestamping, three USB 2.0 high-speed ports (two host, one device), a 12-bit parallel capture interface, hardware AES/SHA/TDES/TRNG cryptography accelerators, and a resistive-touchscreen controller. The device operates from 1.08 V to 1.32 V core and supports 1.2 V, 1.8 V, and 3.3 V I/O banks, allowing mixed-voltage interfacing without external level shifters.
The SAMA5D3 architecture pairs the Cortex-A5 core with a multi-layer AHB bus matrix that allows simultaneous DMA, LCD refresh, and Ethernet traffic without CPU intervention. The DDR2/LPDDR/LPDDR2 memory controller supports up to 1 GB of external RAM, while the NAND Flash controller includes 24-bit ECC for reliable boot from raw NAND. The peripheral DMA controller has 24 channels, offloading data movement from the Cortex-A5 core and freeing CPU cycles for application logic.
Typical applications include industrial human-machine interfaces (HMIs), building automation gateways, smart energy concentrators, point-of-sale terminals, medical patient monitors, and connected IoT edge controllers. The integrated display controller and touchscreen make it especially suited for graphical user-interface products requiring a rich Linux or Android user experience.
When designing with this part, place four 0.1 µF and 4.7 µF decoupling capacitors within 5 mm of the LFBGA power balls and route the DDR2 address/clock nets with matched lengths to maintain signal integrity. The JTAG/SWD debug port is essential for early bring-up; pull the NRST line high with a 10 kΩ resistor and add a 1 nF reset capacitor to meet the datasheet rise-time specification.
This page synthesizes distributor pricing, same-family drop-in alternatives within the SAMA5D3 family, and practical PCB design notes not found on the Microchip product page.
Drop-in alternatives for ATSAMA5D35A-CU — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ATSAMA5D35A-CU (same form factor and footprint) — differing in USB, Package, Ethernet, LCD Controller, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ATSAMA5D34A-CU
✅ Drop-In✓ In Stock
$9.62 / Unit
View Datasheet →ATSAMA5D31A-CU
✅ Drop-In✓ In Stock
$5.65 / Unit
View Datasheet →ATSAMA5D35A-CUR
✅ Drop-In✓ In Stock
$15 / Unit
View Datasheet →ATSAMA5D35A-CU Maximum Ratings & Electrical Characteristics
| Core Architecture | ARM Cortex-A5 (ARMv7-A) |
| Maximum CPU Clock | 536 MHz |
| DMIPS Performance | 850 DMIPS |
| Instruction Cache | 32 KB |
| Data Cache | 32 KB |
| Internal SRAM | 128 KB |
| Internal ROM | 160 KB |
| Floating Point Unit | VFPv4 (single and double precision) |
| Core Voltage | 1.08 V to 1.32 V |
| I/O Voltage | 1.2 V / 1.8 V / 3.3 V |
| Package | 324-LFBGA (15x15 mm) |
| Operating Temperature | -40 °C to +85 °C (industrial) |
| Low-Power Mode Consumption | < 0.5 mW (retention) |
| External Memory Interface | DDR2 / LPDDR / LPDDR2 up to 1 GB |
| NAND Flash Controller | Yes, 24-bit ECC |
| Ethernet | 2x GMAC 10/100/1000 Mbps with IEEE 1588 |
| USB | 3x USB 2.0 High-Speed (2 host, 1 device) |
| Display Controller | LCD TFT up to 2048x2048 |
| Cryptography | AES, SHA, TDES, TRNG |
| Touchscreen Controller | Yes, 4/5-wire resistive |
| RoHS Status | Compliant |
ATSAMA5D35A-CU Pin Configuration
| Pin A1 | VDDOSC — Oscillator power supply |
| Pin A2 | XIN — Crystal oscillator input |
| Pin A3 | XOUT — Crystal oscillator output |
| Pin A4 | VDDANA — Analog power supply |
| Pin A5 | ADVREF — ADC reference voltage |
| Pin B1 | VDDCORE — Core voltage supply (1.08-1.32 V) |
| Pin B2 | GND — Ground |
| Pin B3 | NRST — System reset (active low) |
| Pin B4 | TDI — JTAG test data in |
| Pin B5 | TDO — JTAG test data out |
| Pin C1 | TMS — JTAG test mode select |
| Pin C2 | TCK — JTAG test clock |
| Pin C3 | RTCK — JTAG return test clock |
| Pin C4 | JTAGSEL — JTAG selection |
| Pin C5 | ERASE — Flash erase (active high) |
Typical Applications
ATSAMA5D35A-CU is suitable for 6 applications: Industrial Human-Machine Interface (HMI), Building Automation Gateway, Smart Energy Concentrator, Point-of-Sale (POS) Terminal, Medical Patient Monitor, Connected IoT Edge Controller.
Industrial Human-Machine Interface (HMI)
The ATSAMA5D35A-CU fits industrial HMI panels because it integrates a hardware LCD TFT controller (up to 2048x2048) and a 4/5-wire resistive touchscreen controller in the same LFBGA-324 package, removing the need for an external graphics or touch IC. The 536 MHz Cortex-A5 core runs Linux comfortably with Qt or Crank Storyboard for rich operator dashboards, while the dual Gigabit Ethernet with IEEE 1588 timestamping bridges to fieldbus networks (Profinet, EtherCAT slave) with sub-microsecond synchronization. The industrial -40 °C to +85 °C temperature grade allows deployment inside unheated control cabinets.
Recommended
Building Automation Gateway
In a building-automation gateway the ATSAMA5D35A-CU acts as the protocol-translation brain, converting between BACnet/IP, Modbus TCP, KNX, and MQTT using its dual Gigabit Ethernet with IEEE 1588 timestamping and three USB 2.0 ports for wireless radio dongles (Wi-Fi, LoRa, Zigbee). The 128 KB of internal SRAM plus 1 GB of external DDR2 keeps the TCP/IP stack responsive under heavy load, while the AES/SHA/TRNG accelerators secure OTA firmware updates for BACnet/SC or Matter deployments. Low-power retention below 0.5 mW keeps standby energy consumption at bay for green-building certifications.
Recommended
Smart Energy Concentrator
The ATSAMA5D35A-CU is an ideal concentrator for smart-meter networks: its two GMACs segment the home-area network (HAN) from the neighborhood-area network (NAN), while the Cortex-A5 runs the DLMS/COSEM stack and aggregates 100+ meter readings. Hardware AES/SHA and the true random number generator (TRNG) satisfy IEC 62056 and Common Criteria security requirements for utility-grade meters. The 0.5 mW retention mode keeps the device on standby during power outages while a supercapacitor-backed RTC preserves measurement history.
Recommended
Point-of-Sale (POS) Terminal
Retail POS terminals benefit from the ATSAMA5D35A-CU's combination of an LCD TFT controller for the customer-facing display, USB 2.0 host ports for barcode scanners and receipt printers, and a 10/100/1000 Ethernet port for IP-based payment terminals. The Cortex-A5 runs Android or Linux at 536 MHz with enough headroom for PCI-PTS encrypted PIN-pad drivers and EMV contactless stacks. Hardware AES/SHA accelerators offload TLS handshake and point-to-point encryption (P2PE) workloads, keeping transaction latency below one second end to end.
Recommended
Medical Patient Monitor
Medical patient monitors require a 32-bit application processor that can run a real-time OS, drive a high-resolution color TFT, and securely log patient data - all of which the ATSAMA5D35A-CU delivers on the Cortex-A5 core at 536 MHz. The integrated LCD controller (2048x2048 max) supports high-DPI medical-grade displays, while the touchscreen controller removes a separate component on the bill of materials. Hardware AES/SHA and the secure boot ROM (with TRNG) help satisfy FDA cybersecurity guidance and IEC 62443 for connected medical devices.
Recommended
Connected IoT Edge Controller
The ATSAMA5D35A-CU is well matched to edge controllers that aggregate sensor data, run local analytics, and publish to cloud brokers over MQTT or OPC-UA. The dual Gigabit Ethernet segments the device network from the cloud uplink, while three USB 2.0 high-speed ports accept cellular modems, Wi-Fi 6 adapters, or LoRaWAN concentrators. The Cortex-A5 + VFPv4 hardware floating-point unit accelerates TensorFlow Lite Micro inferences, and the AES/SHA/TRNG block secures TLS 1.3 sessions to AWS IoT Core or Azure IoT Hub without external crypto ICs.
Recommended
Recommended Products Summary
Engineering reference data for ATSAMA5D35A-CU — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ATSAMA5D34A-CU | ATSAMA5D31A-CU | ATSAMA5D35A-CUR |
|---|---|---|---|---|
| Package | 324-LFBGA (15x15) | 324-LFBGA (15x15) | 324-LFBGA (15x15) | 324-LFBGA (15x15) |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| CPU Core | ARM Cortex-A5 | ARM Cortex-A5 | ARM Cortex-A5 | ARM Cortex-A5 |
| Maximum Clock | 536 MHz | 536 MHz | 536 MHz | 536 MHz |
| Internal SRAM | 128 KB | 128 KB | 128 KB | 128 KB |
| Gigabit Ethernet Ports | 2 | 2 | 0 (single 10/100 only) | 2 |
| USB 2.0 High-Speed Ports | 3 (2 host + 1 device) | 2 (1 host + 1 device) | 2 (1 host + 1 device) | 3 (2 host + 1 device) |
| LCD Controller | Yes (2048x2048) | Yes (2048x2048) | No | Yes (2048x2048) |
| Touchscreen Controller | Yes (4/5-wire resistive) | Yes (4/5-wire resistive) | No | Yes (4/5-wire resistive) |
| Hardware Cryptography | AES, SHA, TDES, TRNG | AES, SHA, TDES, TRNG | AES, SHA, TRNG (no TDES) | AES, SHA, TDES, TRNG |
Key Differentiators
- Higher USB host port count than ATSAMA5D34A-CU (vs ATSAMA5D34A-CU)
- Image Sensor Interface (ISI) for camera input (vs ATSAMA5D31A-CU)
- TDES block for legacy banking/government protocols (vs ATSAMA5D31A-CU)
Design Notes
Estimated: at 536 MHz full CPU load, 3.3 V I/O active, and 2x GMAC link-up, the ATSAMA5D35A-CU draws approximately 1.5 W from the 1.2 V core rail plus 0.8 W from the 3.3 V I/O rail (per typical power-consumption curves in the SAMA5D3 datasheet). Place four 4.7 µF X7R bulk capacitors and sixteen 0.1 µF X7R decoupling capacitors within 5 mm of the LFBGA power balls to keep core-voltage ripple below 50 mVpp under dynamic load transitions. Enable the DDR2 self-refresh mode in the PMC before entering ULP0 retention; the 0.5 mW retention spec assumes DDR2 is in self-refresh.
Estimated: at 2.3 W total dissipation in the 324-LFBGA package, the junction-to-ambient thermal resistance of 25 °C/W (with a 4-layer JEDEC JESD51-7 board and 0 m airflow) gives a 58 °C temperature rise above ambient. Inside an industrial enclosure with 70 °C ambient, this places the junction near 128 °C - well above the 125 °C maximum. For sealed enclosures, add a copper heat-spreader under the BGA or vent the enclosure to keep Tj below 100 °C for long-term reliability. The exposed-die LFBGA benefits from thermal vias in the PCB land pattern.
Route the DDR2 address, command, clock, and data nets with length matching within ±25 mil (0.635 mm) and 50 Ω controlled impedance referenced to GND. Use fly-by topology for SDRAM clocks with the optional DDR2 write-deskew byte-lane calibration loaded from the SAMA5D3 at91bootstrap firmware. The reference clock trace to the Ethernet PHY must be under 25 mm and isolated from switching-power lines by at least 3W to avoid coupling jitter into the GMAC; the Ethernet differential pairs (MDI) require 100 Ω differential impedance and 90 Ω common-mode choke footprints per IEEE 802.3.
Do not leave the NRST pin floating; pull it to VDDIO with a 10 kΩ resistor and add a 1 nF capacitor to GND to meet the 1 ms minimum reset pulse. The JTAGSEL pin must be tied to GND through a 10 kΩ resistor for normal Cortex-A5 debug; leaving it open selects the boundary-scan mode and prevents JTAG connection. When booting from NAND, the 24-bit ECC hardware block must be enabled in the PMECC configuration register before the first page read, or boot fails silently on initial bad-block scans.
Compliance Information
RoHS and REACH compliance per Microchip material declaration. Not AEC-Q100 qualified - automotive applications should evaluate the SAMA5D2x automotive grade or external ASIL-D MCU companion. Lead-free and halogen-free per Microchip product page. Conflict-minerals compliance statement available from Microchip.
