ATSAMA5D26A-CUR - 500MHz Cortex-A5 MPU, 289-LFBGA | Microchip
MPN: ATSAMA5D26A-CUR β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $21.5 | $21.50 |
| 10 | $19.85 | $198.50 |
| 100 | $17.95 | $1,795.00 |
| 500 | $15.8 | $7,900.00 |
| 1,000 | $14.2 | $14,200.00 |
ATSAMA5D26A-CUR Overview
An ARM Cortex-A5 MPU is a microprocessor unit built on the ARMv7-A architecture - a Harvard-style superscalar core with MMU, caches, and optional NEON/FPU. MPUs run full operating systems (Linux, Android, RTOS) on external memory, distinguishing them from microcontrollers (MCUs) which typically execute firmware from internal flash with no MMU. The Cortex-A5 sits in the low-power end of the application-processor hierarchy (Cortex-A5 -> Cortex-A family -> ARM application processors -> 32-bit embedded processors -> semiconductors), targeting HMI, IoT gateways, and industrial control where deterministic power and small die area matter more than raw performance.
Key features include the SAMA5D2 series' hardware cryptography block (AES, SHA, TRNG), secure boot, tamper detection pins, and an LCD controller supporting up to WXGA. The 289-LFBGA package exposes the full SAMA5D26 signal set including dual CAN-FD, three FLEXCOMs (USART/SPI/TWI), two I2S, and 12-bit ADC, enabling direct connection to industrial sensors, displays, and wired networking without external bridges.
Architecturally, the SAMA5D26 uses a single-issue, in-order Cortex-A5 core with NEON and FPU, fed by 32 KB instruction and 32 KB data caches backed by a 128 KB system SRAM. The Advanced Interrupt Controller (AIC) and a frequency-scalable LDO allow run, idle, and ultra-low-power modes, while the peripheral DMA controller offloads data movement from the CPU. The hardware crypto block accelerates AES up to 256-bit, SHA-1/256, and provides a true random number generator suitable for TLS key exchange.
Typical applications include industrial HMI panels, smart energy gateways, building automation controllers, POS terminals, and IoT edge nodes running Linux. Designers choose the SAMA5D26 over Cortex-M4/M7 MCUs when an MMU and OS are required, and over Cortex-A53/A72 MPUs when power budget or BOM cost dominates.
Design consideration: route DDR signals first with length-matched impedance-controlled traces, and dedicate at least one full ground plane beneath the BGA. Decouple each VDD/VBAT/VDDANA pin with a 100 nF ceramic cap as close to the balls as practical.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, accelerating component selection for embedded Linux designs.
Drop-in alternatives for ATSAMA5D26A-CUR β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ATSAMA5D26A-CUR (same form factor and footprint) β differing in Ethernet, Package, USB, Operating Temperature, Display Controller.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
ATSAMA5D26A-CU
β Drop-Inπ Reference alternative (not in catalog)
ATSAMA5D26A-CN
β Drop-Inβ In Stock
$15.2 / Unit
View Datasheet βATSAMA5D26B-CUR
β Drop-Inβ In Stock
$9.55 / Unit
View Datasheet βATSAMA5D24C-CUR
β Drop-Inβ In Stock
$10.2 / Unit
View Datasheet βATSAMA5D24B-CU
β Drop-Inβ In Stock
$10.42 / Unit
View Datasheet βATSAMA5D23A-CUR
β Drop-Inβ In Stock
$8.95 / Unit
View Datasheet βATSAMA5D26A-CUR Maximum Ratings & Electrical Characteristics
| Core Architecture | ARM Cortex-A5 (ARMv7-A) |
| Maximum CPU Clock | 500 MHz |
| Core Count | 1 |
| Bit Width | 32-bit |
| Internal SRAM | 128 KB |
| Internal ROM | 160 KB |
| L1 Instruction Cache | 32 KB |
| L1 Data Cache | 32 KB |
| FPU / NEON | Yes (single-precision FPU + NEON) |
| Memory Interfaces | DDR2, DDR3L, LPDDR2, LPDDR3, QSPI, e.MMC, NAND, NOR |
| External Memory Bus | 16-bit EBI |
| Display Controller | Integrated LCD controller up to WXGA (1366x768) |
| Ethernet | 2x 10/100 Mbps EMAC (GMII/RGMII/MII) |
| USB | 2x USB 2.0 High-Speed Host + 1x USB 2.0 Device/Host |
| CAN | 2x CAN-FD |
| Crypto Accelerator | AES, SHA, TRNG, secure boot |
| ADC | 12-bit, 1 Msps, up to 12 channels |
| Package | 289-LFBGA, 14x14 mm, 0.8 mm pitch |
| Supply Voltage (Core) | 1.2 V (typ) |
| Operating Temperature | -40C to +85C (Industrial) |
| Mounting Type | Surface Mount |
| MSL Level | 3 (per JEDEC J-STD-020) |
| RoHS Status | Compliant |
ATSAMA5D26A-CUR 289-lfbga, 14x14 mm, 0.8 mm pitch Pin Configuration Guide
Pin configuration for ATSAMA5D26A-CUR (289-lfbga, 14x14 mm, 0.8 mm pitch package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for ATSAMA5D26A-CUR.
Refer to the datasheet for full pin configuration.
Typical Applications
ATSAMA5D26A-CUR is suitable for 7 applications: Industrial HMI Panel, Smart Energy Gateway, Building Automation Controller, POS Terminal / Payment Device, IoT Edge Gateway with Linux, Medical Device Controller, Industrial Printer Controller.
Industrial HMI Panel
The ATSAMA5D26A-CUR's 500 MHz Cortex-A5 core plus integrated LCD controller (WXGA at 1366x768) makes it ideal for industrial human-machine interface panels driving 7-10 inch capacitive-touch TFTs. Its 128 KB system SRAM plus external DDR3L handles Qt/Weston graphics stacks smoothly while the dual 10/100 EMAC and dual CAN-FD connect directly to PLC field buses without external bridges. Power consumption stays under 1 W active, allowing fanless sealed enclosures. The 289-LFBGA package fits compact panel PCBs.
Recommended
Smart Energy Gateway
The ATSAMA5D26A-CUR serves as the main application processor in smart energy gateways aggregating data from electricity, gas, and water meters over M-Bus, LoRa, or Zigbee. The hardware AES/SHA crypto accelerator plus TRNG accelerates TLS 1.3 handshakes for secure cloud uploads, while the 500 MHz Cortex-A5 with MMU runs full Linux for MQTT, DLMS/COSEM, or OpenADR stacks. Dual CAN-FD interfaces support EV charging and DER aggregation per IEC 61850.
Recommended
Building Automation Controller
In BACnet/Modbus building controllers, the ATSAMA5D26A-CUR runs Linux with the Niagara or openBEM stack while its dual CAN-FD, three FLEXCOM, and dual EMAC interface directly to HVAC actuators, lighting DALI buses, and access-control readers. The industrial -40C to +85C temperature range suits unconditioned mechanical rooms, and the hardware crypto block secures TLS tunnels to cloud BMS dashboards. Industrial operating temperature ensures reliable operation in plant rooms.
Recommended
POS Terminal / Payment Device
POS terminals benefit from the ATSAMA5D26A-CUR's hardware AES/SHA plus TRNG for PCI PTS 4.x secure PIN entry and EMV contactless payments. The 500 MHz Cortex-A5 handles Linux-based Android derivatives, NFC reader IC interfaces via SPI, and printer control, all from a single chip. Integrated LCD controller drives main operator display while a second SPI display can serve the customer-facing screen. Low power consumption extends battery life in mobile POS form factors.
Recommended
IoT Edge Gateway with Linux
Edge gateways running Docker containers or K3s on Linux use the ATSAMA5D26A-CUR to aggregate sensor data via RS-485, Modbus, CAN, and 1-Wire. The 500 MHz core plus 128 KB SRAM plus external DDR3L supports containerized workloads, while the dual 10/100 EMAC provides segregated WAN/LAN. Industrial -40C to +85C operation suits outdoor enclosures, and the LFBGA package enables compact gateway designs.
Recommended
Medical Device Controller
Medical device controllers use the ATSAMA5D26A-CUR to drive color TFTs showing patient data while running Linux for FDA-cleared application logic. The hardware AES/SHA block plus secure boot provides tamper-resistant firmware validation, while the 12-bit ADC interfaces directly with sensor front-ends. Industrial temperature and the 14x14 mm BGA package enable compact handheld designs for patient monitors and infusion pumps. Note: medical certification requires additional IEC 60601 system-level compliance beyond the IC itself.
Recommended
Industrial Printer Controller
Industrial label and barcode printers use the ATSAMA5D26A-CUR to drive stepper motors for label feed and printhead control, plus the integrated LCD for operator interface and the EMAC for fleet management. The 500 MHz Cortex-A5 with NEON accelerates image rasterization for thermal printheads, while QSPI flash holds font and barcode libraries. CAN-FD interfaces with cutter and applicator subsystems in labeling production lines.
Recommended
Recommended Products Summary
Engineering reference data for ATSAMA5D26A-CUR β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ATSAMA5D26A-CU | ATSAMA5D26A-CN | ATSAMA5D26B-CUR | ATSAMA5D24C-CUR | ATSAMA5D24B-CU | ATSAMA5D23A-CUR |
|---|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 289-LFBGA (14x14 mm) | 289-LFBGA (14x14 mm) - same | 289-LFBGA (14x14 mm) - same | 289-LFBGA (14x14 mm) - same | 289-LFBGA (14x14 mm) - same | 289-LFBGA (14x14 mm) - same | 289-LFBGA (14x14 mm) - same |
| CPU Core | ARM Cortex-A5 500 MHz | ARM Cortex-A5 500 MHz | ARM Cortex-A5 500 MHz | ARM Cortex-A5 500 MHz | ARM Cortex-A5 500 MHz | ARM Cortex-A5 500 MHz | ARM Cortex-A5 500 MHz |
| Internal SRAM | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB |
| LCD Controller | Yes (WXGA) | Yes (WXGA) | Yes (WXGA) | Yes (WXGA) | Yes (reduced resolution) | Yes (reduced resolution) | Yes (reduced resolution) |
| Crypto Accelerator | AES/SHA/TRNG + secure boot | AES/SHA/TRNG + secure boot | AES/SHA/TRNG + secure boot | AES/SHA/TRNG + secure boot | AES/SHA/TRNG + secure boot | AES/SHA only | AES/SHA/TRNG + secure boot |
| CAN-FD | 2x CAN-FD | 2x CAN-FD | 2x CAN-FD | 2x CAN-FD | 2x CAN-FD | 2x CAN | 2x CAN-FD |
| Temperature Grade | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) |
| Packaging Form | Tape & Reel | Tray | Tray | Tape & Reel | Tape & Reel | Tray | Tape & Reel |
Key Differentiators
- Hardware AES/SHA crypto with secure boot and tamper detection at single-chip price point (vs ATSAMA5D24B-CU)
- Full LCD controller supporting WXGA panels with hardware overlay (vs ATSAMA5D24C-CUR)
- Dual CAN-FD interfaces for automotive and industrial field bus (vs ATSAMA5D24B-CU)
Design Notes
The 289-LFBGA package has 0.8 mm ball pitch on a 14x14 mm body; design with at least 4 PCB layers including one solid ground plane directly beneath the BGA. Use laser-drilled microvias (0.1 mm) with stacked-via structure to fan out the inner rows, and route DDR signals with length-matched +/-25 mil traces and 50 ohm single-ended / 100 ohm differential impedance. Place 100 nF X7R 0201 decoupling capacitors on every VDD/VDDANA/VDDPLL ball within 3 mm, plus bulk 4.7 uF X5R 0402 capacitors at each power domain boundary.
The SAMA5D26 requires multiple voltage rails: VDD1V2 (core, 1.2 V typ up to 1 A), VDD3V3 (I/O), VDDANA (ADC/PLL, low noise), and VDDBU (RTC backup, ~1.5 uA standby). Use a high-PSRR LDO such as the MIC2800 or TPS7A4701 for VDDANA to keep ADC noise below 1 LSB at 12-bit resolution. Sequence the rails so VDD1V2 powers up within 50 ms of VDD3V3; hold the SAMA5D26 in reset via NRST until all rails are stable.
Estimated: at 500 MHz core clock with peripheral activity, typical power dissipation is 350-500 mW with peak DDR I/O at 700 mW; the 289-LFBGA has theta_JA of approximately 25 C/W on a 4-layer 1 oz PCB, giving a 9-13 C junction rise above ambient at full load. For sealed industrial enclosures above +60 C ambient, provide a 2-layer copper flood on the top side beneath the BGA and thermal vias to the inner ground plane. Junction temperature must stay below +125 C; thermal shutdown engages at +130 C typical.
Three common pitfalls: (1) Failing to disable the secure boot in development flows - the boot ROM expects a signed image, so use the SAM-BA boot mode via NAND/QSPI for initial prototype bring-up; (2) Mixing DDR3L and LPDDR3 in the same PCB - the SAMA5D26 supports one or the other, not both simultaneously, and the pinout is incompatible; (3) Forgetting to connect VDDBU to a coin-cell or supercap when designing RTC retention - the backup domain draws ~1.5 uA but is essential for tamper detection.
Place the 24 MHz main crystal within 5 mm of XIN/XOUT with a load capacitor ground reference to the same ground as the PLL ground pin. Keep high-speed USB differential pairs (90 ohm differential, 6 mil trace/space) at least 3 mm away from LCD data lines to avoid EMI coupling. The DDR clock trace must be length-matched to the address/command group within 25 mil; use fly-by routing for address signals to minimize reflections. Place the Ethernet PHY within 50 mm of the EMAC pins with length-matched MII/RGMII traces.
Compliance Information
RoHS and REACH compliant per Microchip product page; lead-free reflow compatible with JEDEC J-STD-020 MSL3 profile. Not AEC-Q100 qualified (industrial grade only); the SAMA5D2 family does not include an AEC-Q100 variant. Halogen-free status not explicitly stated in verified data.
