CD40161B-MIL - CMOS Sync 4-Bit Binary Counter | Texas Instruments
MPN: CD40161B-MIL ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
CD40161B-MIL Overview
A synchronous programmable counter is a digital sequential logic device that advances through a binary counting sequence on each rising clock edge while allowing any 4-bit value to be parallel-loaded via preset inputs. Within the logic IC hierarchy, counters are fundamental building blocks of the broader family of sequential logic and digital timing devices, sitting alongside shift registers and flip-flops as core building blocks for sequencing and frequency division in digital systems.
Key features include fully static operation down to DC, standardized symmetrical output characteristics meeting JEDEC Tentative Standard No. 13B for B-series CMOS devices, and a fanout of 1 LSTTL load for direct interfacing with other logic families. The asynchronous clear resets all outputs to zero immediately regardless of clock state, and the ripple carry output enables straightforward cascading of multiple stages into wider counters.
Technically, the CD40161B uses CMOS technology with buffered outputs and input protection diodes to VDD and VSS, providing low static power consumption and high noise immunity typical of the CD4000B series. Typical propagation delay is 160ns at 5V, and the device is functionally equivalent to and pin-compatible with the TTL 74LS161 counter.
Typical applications include frequency dividers, programmable binary counting, counter control/timers, event counters, and state machines in industrial control, test equipment, and aerospace electronics where hermetic packaging and the military temperature range are mandatory.
A key design consideration: tie the asynchronous clear input to VDD when unused to prevent spurious resets, and provide clean clock edges to avoid double counting.
This page synthesizes verified datasheet parameters, drop-in family alternatives, pricing tiers, and practical design notes not consolidated in the manufacturer datasheet.
Drop-in alternatives for CD40161B-MIL — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
CD40161BF3A
✅ Drop-In📋 Reference alternative (not in catalog)
CD40161BE
✅ Drop-In📋 Reference alternative (not in catalog)
CD40163BF3A
✅ Drop-In📋 Reference alternative (not in catalog)
CD40160BF3A
✅ Drop-In📋 Reference alternative (not in catalog)
CD40162BF3A
✅ Drop-In📋 Reference alternative (not in catalog)
CD40161B-MIL Maximum Ratings & Electrical Characteristics
| Logic Function | CMOS Synchronous Programmable 4-Bit Binary Counter with Asynchronous Clear |
| Logic Family | CD4000B Series CMOS |
| Supply Voltage Range | 3 V to 18 V |
| Operating Temperature Range | -55C to +125C |
| Maximum Clock Frequency | 5.5 MHz at 5 V |
| Propagation Delay | 160 ns typ at 5 V |
| Output Fanout | 1 LSTTL load |
| Operation Mode | Fully static, DC to fmax |
| Reset Type | Asynchronous clear |
| Carry Output | Ripple carry output (RCO) for cascading |
| Standard Compliance | JEDEC Tentative Standard No. 13B (B-series CMOS) |
| Military Screening | Meets MIL-STD-883 requirements |
| Package | 16-lead hermetic dual-in-line ceramic (F3A suffix) |
| Mounting Type | Through Hole |
| Input Protection | Diodes to VDD and VSS on all inputs |
| TTL Compatibility | Functionally equivalent and pin-compatible with 74LS161 |
CD40161B-MIL Pin Configuration
| Pin 1 | CLR — Asynchronous clear (active low) - resets all outputs to 0 |
| Pin 2 | CLK — Clock input (rising edge triggered) |
| Pin 3 | P0 (A) — Parallel data input, bit 0 |
| Pin 4 | P1 (B) — Parallel data input, bit 1 |
| Pin 5 | P2 (C) — Parallel data input, bit 2 |
| Pin 6 | P3 (D) — Parallel data input, bit 3 |
| Pin 7 | ENP (CEP) — Count enable parallel input |
| Pin 8 | VSS — Ground (negative supply) |
| Pin 9 | LOAD (PE) — Parallel load enable (active low, synchronous) |
| Pin 10 | ENT (CET) — Count enable trickle input |
| Pin 11 | Q3 (QD) — Counter output, bit 3 (MSB) |
| Pin 12 | Q2 (QC) — Counter output, bit 2 |
| Pin 13 | Q1 (QB) — Counter output, bit 1 |
| Pin 14 | Q0 (QA) — Counter output, bit 0 (LSB) |
| Pin 15 | RCO — Ripple carry output for cascading (high at terminal count with ENT high) |
| Pin 16 | VDD — Positive supply, 3 V to 18 V |
Typical Applications
CD40161B-MIL is suitable for 6 applications: Frequency Division Chains, Programmable Binary Counting, Counter Control / Timers, Event Counters in Test Equipment, State Machines in Aerospace Electronics, Digital Clocks and Display Timing.
Frequency Division Chains
The CD40161B-MIL divides an input clock by any power-of-two value up to 16 per stage using the ripple carry output to cascade stages synchronously. Its fully static CMOS operation down to DC means the divider holds its count with a stopped clock - useful in systems that gate the clock to save power. The 5.5MHz maximum clock at 5V accommodates most industrial clock sources, and the wide 3V to 18V supply range lets designers match the divider rail to downstream logic. In military and aerospace systems, the hermetic F3A ceramic package and -55C to +125C range ensure stable divide ratios across temperature, and the asynchronous clear gives an immediate, deterministic start-of-chain reset independent of clock phase.
Recommended
Programmable Binary Counting
Because the four preset inputs load any 4-bit value synchronously, the CD40161B-MIL implements programmable modulo-N counters: load a start value and detect terminal count to produce a divide-by-N output where N is set by DIP switches or register bits. At 5V the 5.5MHz clock ceiling and 160ns typical propagation delay suit timing generators up to the low-MHz range, while 1 LSTTL-load fanout drives adjacent TTL/CMOS logic directly. The -MIL hermetic ceramic package supports military program requirements, and the JEDEC No. 13B standardized symmetrical output characteristics give predictable interface behavior across the CD4000B family used in the same system.
Recommended
Counter Control / Timers
Event sequencers and interval timers in industrial control use the CD40161B-MIL to step through states on each rising clock edge, with the asynchronous clear providing instant restart on fault or operator reset. The synchronous parallel load allows a controller to inject a new starting state mid-sequence without stopping the clock. With 3V to 18V supply tolerance the counter rides through supply sag on industrial rails, and CMOS noise immunity keeps counts stable in electrically noisy factory environments. The hermetic ceramic package extends reliability to outdoor and aerospace timer modules where condensation and contaminant exposure would degrade plastic-packaged devices over long service intervals.
Recommended
Event Counters in Test Equipment
Bench and automated test instruments employ cascaded CD40161B-MIL stages as totalizing counters, accumulating pulses from sensors, gates, or prescalers. The ripple carry output plus shared-clock topology keeps cascaded stages synchronous to within one propagation delay, minimizing Skew-induced count errors. The asynchronous clear enables a per-measurement reset pulse. At 5V the 5.5MHz input limit defines the top countable rate; a faster prescaler ahead of the chain handles higher frequencies. The -55C to +125C military range and hermetic package allow deployment in field test sets and flight-line equipment where temperature excursions and shelf life of decades are normal requirements.
Recommended
State Machines in Aerospace Electronics
Small aerospace sequencers use the CD40161B-MIL as a state register: the 4-bit count encodes up to 16 states, and external decode logic drives the asynchronous clear and parallel load for conditional transitions. Operation to 18V gives generous noise margins over spacecraft and avionics 12V-class internal rails, and static CMOS design consumes negligible current between clock edges - important for power-limited platforms. MIL-STD-883 conformance and the hermetic F3A ceramic package align with aerospace procurement requirements, while pin compatibility with the broader CD40160B/40161B/40162B/40163B family lets one PCB footprint accept binary or decade, synchronous- or asynchronous-clear variants during design trade studies.
Recommended
Digital Clocks and Display Timing
The CD40161B-MIL stages chain into hours/minutes/seconds dividers and scan-rate generators for digital clocks and display drivers. The CD40160B decade variant (same package and pinout) handles BCD positions, with the CD40161B handling binary divisions. The 160ns typical propagation delay at 5V is negligible against human-perceivable timing, and rail-to-rail CMOS outputs directly drive decoder inputs with 1 LSTTL-load fanout. Wide supply tolerance supports battery-backed operation from 3V, retaining time during main-power loss with static zero current between clock edges. Hermetic military packaging suits fixed-installation clocks in naval and ground-defense environments with multi-decade service expectations.
Recommended
Recommended Products Summary
Engineering reference data for CD40161B-MIL — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | CD40161BF3A | CD40161BE | CD40163BF3A | CD40160BF3A |
|---|---|---|---|---|---|
| Package | 16-lead hermetic ceramic DIP (F3A) | 16-lead hermetic ceramic DIP (F3A) - same | 16-lead plastic DIP (E) - same DIP-16 footprint | 16-lead hermetic ceramic DIP (F3A) - same | 16-lead hermetic ceramic DIP (F3A) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Counting Sequence | Binary (modulo-16) | Binary (modulo-16) | Binary (modulo-16) | Binary (modulo-16) | Decade / BCD (modulo-10) |
| Clear Type | Asynchronous clear | Asynchronous clear | Asynchronous clear | Synchronous clear | Asynchronous clear |
| Supply Voltage Range | 3 V to 18 V | 3 V to 18 V | 3 V to 18 V | 3 V to 18 V | 3 V to 18 V |
| Military Screening | MIL-STD-883, hermetic package | MIL-STD-883, hermetic | None (commercial plastic) | MIL-STD-883, hermetic | MIL-STD-883, hermetic |
| TTL Equivalent | 74LS161 (pin-compatible) | 74LS161 | 74LS161 | 74LS163 | 74LS160 |
Key Differentiators
- MIL-STD-883 military qualification with hermetic ceramic package (vs CD40161BE)
- Asynchronous clear for immediate reset (vs CD40163BF3A)
- Sole qualified source for the hermetic binary version (vs CD40160BF3A)
Design Notes
Tie the asynchronous CLR input to VDD when unused. Because CLR acts immediately and independently of the clock, a floating or slow-rising CLR line picks up noise and causes random counter resets that are extremely difficult to diagnose in the field. If a reset function is needed, derive it from a supervisor IC or RC network with a fast, clean edge. Similarly, the synchronous LOAD pin is active low - pull it high through a resistor when parallel loading is not used, so board leakage cannot assert load mode.
Decouple VDD with a 0.1uF ceramic capacitor placed within a few millimeters of pin 16 to VSS (pin 8). CD4000B CMOS draws very low static current, but clock transitions cause supply transients proportional to load capacitance and frequency; in cascaded counters sharing a clock, simultaneous output switching on multiple stages injects current spikes into the ground rail. Also respect input voltage limits: all inputs, including CLK and CLR, must stay within VSS-0.5V to VDD+0.5V - the protection diodes to VDD and VSS conduct otherwise, and inputs must never be driven when VDD is absent.
Provide clean, fast clock edges. CD4000B inputs have a defined switching threshold, and a slowly rising clock edge traversing the threshold region can double-count on noise. Use a Schmitt-trigger buffer (for example a CD4093 gate) for clocks derived from RC oscillators or long wires. When cascading via RCO to ENT, keep the interconnect short; the RCO-to-ENT path plus propagation delay sets the maximum cascaded clock rate below the single-stage 5.5MHz figure at 5V.
Compliance Information
Military hermetic ceramic package (F3A) per TI datasheet; meets MIL-STD-883 requirements. Lead finish and RoHS/REACH status for the -MIL suffix were not stated in the retrieved data - verify on the TI product page before ordering.
