CD74ACT163 - 4-Bit Sync Binary Counter 5V | Texas Instruments
MPN: CD74ACT163 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0.75 | $0.75 |
| 10 | $0.65 | $6.50 |
| 100 | $0.52 | $52.00 |
| 500 | $0.43 | $215.00 |
| 1,000 | $0.36 | $360.00 |
Drop-in alternatives for CD74ACT163 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
CD74ACT163E
β Drop-Inπ Reference alternative (not in catalog)
CD74ACT163M
β Drop-Inπ Reference alternative (not in catalog)
CD74ACT163M96
β Drop-Inπ Reference alternative (not in catalog)
74ACT163M
β Drop-Inπ Reference alternative (not in catalog)
CD74ACT163 Maximum Ratings & Electrical Characteristics
| Function | 4-bit synchronous presettable binary counter with synchronous reset |
| Logic Family | ACT (Advanced CMOS, TTL-compatible inputs) |
| Supply Voltage | 4.5 V to 5.5 V |
| Input Compatibility | TTL voltage compatible |
| Clock Edge | Positive edge triggered |
| Reset Type | Synchronous |
| Load Type | Synchronous parallel load |
| Carry Look-ahead | Internal, with ripple carry output (RCO) |
| Cascading | Yes, RCO to ENT for n-bit counters |
| Package | 16-SOIC |
| Mounting Type | Surface Mount |
| Elements / Bits | 1 element, 4 bit |
| Operating Temperature | [DATA_NEEDED: operating temperature range per package suffix] |
| RoHS Status | [DATA_NEEDED: RoHS status per package suffix] |
| Military Version | CD54ACT163 available (military grade) |
| Datasheet Revision | Rev. B |
CD74ACT163 Pin Configuration
| Pin 1 | CLR β Synchronous clear (active low) - resets all outputs on next clock edge |
| Pin 2 | CLK β Clock input, positive edge triggered |
| Pin 3 | A β Parallel data input A |
| Pin 4 | B β Parallel data input B |
| Pin 5 | C β Parallel data input C |
| Pin 6 | D β Parallel data input D |
| Pin 7 | ENP β Count enable P input |
| Pin 8 | GND β Ground |
| Pin 9 | LOAD β Synchronous parallel load (active low) |
| Pin 10 | ENT β Count enable trickle input (also gates RCO) |
| Pin 11 | QD β Counter output D (MSB) |
| Pin 12 | QC β Counter output C |
| Pin 13 | QB β Counter output B |
| Pin 14 | QA β Counter output A (LSB) |
| Pin 15 | RCO β Ripple carry output for n-bit cascading |
| Pin 16 | VCC β Supply voltage, 5V |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
CD74ACT163 is suitable for 6 applications: Frequency Division, Event Counting in Industrial Automation, Address Generation for Memory, Digital Timers and Sequencers, Test and Measurement Instrumentation, Automotive and Legacy 5V System Retrofits.
Frequency Division
The CD74ACT163 divides input clock frequencies by configuring it as a programmable-modulus counter using the synchronous LOAD input and a modulus-detect decoder on the Q outputs. Its internal carry look-ahead keeps propagation short at high clock rates, and the synchronous reset avoids glitch-induced miscounts at the rollover boundary. Wired as a divide-by-N stage, each 4-bit counter provides one nibble; multiple stages cascade via RCO-to-ENT for divide-by-256 or larger. Decouple the 5V rail locally to keep clock edges clean.
Recommended
Event Counting in Industrial Automation
Counting pulses from sensors, encoders, or flow meters is a core industrial task. The CD74ACT163 TTL-compatible inputs interface directly with 5V sensor electronics, while synchronous ENP/ENT gating allows clean count-enable control from a PLC-level gate signal. Its positive-edge clocking counts each event once, and the synchronous load lets a controller preset a starting value at any time. The ACT family trade-off is fixed 5V operation, so level-shift when mixing with 3.3V controllers.
Recommended
Address Generation for Memory
The CD74ACT163 generates sequential memory addresses when cascaded to 8, 12, or 16 bits via RCO-to-ENT connections. The internal carry look-ahead minimizes inter-stage ripple delay, preserving address setup time at the memory device. Synchronous load supports jump-to-address operations for buffer management. Because all bits change coincident with the clock, address bus glitches are eliminated compared to ripple counters, improving margin with fast SRAM or FIFO devices.
Recommended
Digital Timers and Sequencers
The CD74ACT163 forms the counting core of digital timers: cascade stages, decode the terminal count, and reload synchronously for repeating timebases. The synchronous reset permits glitch-free restart of each timing cycle, a key advantage over asynchronous-clear counters that can produce sub-clock-period output spikes. With a stable crystal-derived clock, multi-stage ACT163 chains deliver deterministic intervals for relay sequencing, wash-cycle control, and test-fixture timing.
Recommended
Test and Measurement Instrumentation
Bench instruments and ATE fixtures use the CD74ACT163 as a hardware event counter, prescaler, or state-machine sequencer. Its deterministic synchronous behavior simplifies timing verification, and the military-qualified CD54ACT163 sibling extends use into lab-grade and defense instrumentation. The LOAD input enables rapid presetting to known states between test cycles, and ENT gating allows hardware-suppressed counting during setup phases, all without firmware latency.
Recommended
Automotive and Legacy 5V System Retrofits
In 12V automotive systems with regulated 5V rails, the CD74ACT163 counts encoder pulses or tachometer pulses for gauge and control modules. Although the standard part is not AEC-Q100 qualified, TI Q1 logic family companions on the same board share the 5V domain, and the ACT163's TTL thresholds tolerate automotive-tolerant noise margins. For new automotive designs, verify qualification requirements; for legacy module service and repair, this counter remains a direct fit.
Recommended
Recommended Products Summary
Engineering reference data for CD74ACT163 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | CD74ACT163E | CD74ACT163M | 74ACT163M | 74ACT163N |
|---|---|---|---|---|---|
| Package | 16-SOIC | 16-SOIC - same | 16-SOIC - same | 16-SOIC - same | 16-DIP - different footprint |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments (Rochester/Harris stock) | onsemi | onsemi |
| Counter Bits | 4 bit | 4 bit | 4 bit | 4 bit | 4 bit |
| Reset Type | Synchronous | Synchronous | Synchronous | Synchronous | Synchronous |
| Supply Voltage | 5 V (ACT) | 5 V | 5 V | 5 V | 5 V |
| Input Compatibility | TTL | TTL | TTL | TTL | TTL |
| Cascading Output | RCO | RCO | RCO | RCO | RCO |
| Drop-in Compatibility | Reference | 100% (same suffix family) | 100% | ~90% (verify AC timing) | No (package differs) |
Key Differentiators
- Synchronous reset eliminates clear glitches (vs CD74ACT161)
- Internal carry look-ahead for high-speed cascades (vs CD74HC163)
- Multi-source industry-standard 74163 pinout (vs 74ACT163M (onsemi))
Design Notes
The CLR and LOAD inputs of the CD74ACT163 are synchronous: they take effect only on the next positive clock edge and must be held valid for at least one full clock cycle plus setup time. Designs migrated from asynchronous-clear 74161 counters will behave differently - a short CLR pulse near a clock edge may be missed entirely or, if removed mid-cycle, may cause an off-by-one count.
Place a 0.1uF ceramic decoupling capacitor within 5 mm of the VCC (pin 16) to GND (pin 8) pair. ACT-family clocked logic draws dynamic current on each edge; shared impedance on the 5V rail can couple clock noise into adjacent analog circuitry. For cascaded counters, distribute one capacitor per package and keep the common clock line short with a series termination resistor (22-33 ohm) at the driver if trace length exceeds 10 cm.
In multi-stage cascades, connect RCO of stage N to ENT of stage N+1 with all stages sharing one clock. Do not gate the clock line for enable control - use ENP/ENT instead, per TI application practice for the 74163 family. Clock gating causes skewed edges across stages and violates the fully synchronous assumption that makes the carry look-ahead architecture fast and glitch-free.
Compliance Information
Compliance status varies by package suffix (E vs M vs M96). Verify RoHS/REACH status per suffix on TI.com product pages. Not an AEC-Q100 automotive part.
