DP83826AI - Low-Latency 10/100 Ethernet PHY | TI
MPN: DP83826AI ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4.1 | $4.10 |
| 10 | $3.6 | $36.00 |
| 100 | $3.05 | $305.00 |
| 500 | $2.65 | $1,325.00 |
| 1,000 | $2.35 | $2,350.00 |
DP83826AI Overview
An industrial Ethernet PHY (Physical Layer transceiver) is a specialized transceiver IC that connects an MCU or SoC's MAC (Media Access Controller) to the copper twisted-pair medium via an isolation transformer, performing 10BASE-Te/100BASE-TX line coding, echo cancellation, and clock/data recovery. In the broader system hierarchy, the PHY sits below the MAC layer (Layer 2) of the OSI reference model and above the transformer and RJ-45 magnetics, forming the physical interface that turns serialized MAC data into MLT-3 (100BASE-TX) or differential Manchester-coded (10BASE-Te) signals on the MDI lines. For deterministic real-time protocols such as EtherCAT, Profinet IRT, and SERCOS III, the PHY's transmit and receive pipeline latency must be tightly bounded; the DP83826AI is designed to meet those bounds.
Key differentiating features of the DP83826AI include sub-microsecond deterministic loop latency in 100 Mbps full-duplex mode, low power consumption suitable for distributed sensor nodes, integrated PHY diagnostics including cable diagnostics and link-quality monitoring, support for both MII and RMII bus widths, and an industrial-grade operating range. The 32-VQFN (RHB) package with an exposed thermal pad enables compact board layouts typical of small PLC slices, distributed I/O stations, and motor-control daughterboards where PCB real estate is at a premium.
In typical operation the DP83826AI is paired with an industrial MCU (such as TI's Sitara AM243x family) running an EtherCAT slave stack, with the PHY providing the physical edge to a 100BASE-TX link. The architecture focuses on minimizing store-and-forward buffers in the receive and transmit paths, which is what enables the bounded, jitter-free latency that EtherCAT's distributed clock synchronization demands. Hardware straps allow configuration of master/slave mode, MII vs. RMII selection, and 10/100 Mbps speed without external software intervention in strap-only systems.
Typical applications include EtherCAT slave modules, Profinet IRT devices, industrial servo drives, distributed I/O over industrial Ethernet, and small-form-factor PLCs. Real-world deployments span factory-floor closed-loop motion control, substation automation with IEC 61850, and deterministic sensor networks where IEEE 1588 timing is carried over the same Ethernet link.
When designing with the DP83826AI, pay close attention to magnetics selection (the part requires a 1:1 transformer ratio with a center-tapped primary for 100BASE-TX), PCB layout for the MDI traces (100-ohm differential with controlled impedance), and isolation barrier placement to meet IEC 61800-3 industrial emissions requirements. Use of dedicated magnetics with integrated common-mode chokes is recommended to take full advantage of the device's improved EMC margin relative to DP83826I.
Drop-in alternatives for DP83826AI — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DP83826AI (same form factor and footprint) — differing in Data Rate, MAC Interface, Operating Temperature, Package, Product Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DP83826I
✅ Drop-In📋 Reference alternative (not in catalog)
DP83826AIRHBR
✅ Drop-In📋 Reference alternative (not in catalog)
DP83848KSQ/NOPB
✅ Drop-In✓ In Stock
$3.55 / Unit
View Datasheet →DP83826AI Specifications
| Product Type | Industrial 10/100 Mbps Ethernet PHY |
| Data Rate | 10 Mbps / 100 Mbps (auto-negotiation) |
| Network Standards | IEEE 802.3, 10BASE-Te, 100BASE-TX |
| MAC Interface | MII and RMII |
| Latency Profile | Deterministic, low-latency (optimized for EtherCAT) |
| Supply Voltage | 3.3 V (analog/digital, see datasheet) |
| ESD Rating (Contact) | 8 kV (IEC 61000-4-2 Class A margin on DP83826A) |
| Operating Temperature | -40 C to +85 C (industrial) |
| Package | 32-pin VQFN (RHB) 5x5 mm |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead Finish | Lead-free (NiPdAu, per TI product page) |
| Cable Diagnostics | Yes (TDR-based link diagnostics) |
| Link Quality Monitoring | Yes (SNR + error counters) |
| EMC Performance | Enhanced (Class A margin); improved versus DP83826I |
| Strap for RX_CLK Link Stability | Yes (added on DP83826A vs. DP83826I) |
DP83826AI Pin Configuration
| Pin 1 | VDDA — Analog 3.3 V supply |
| Pin 2 | RX_CLK — Receive clock / strap (link-drop-prevention on 'A' revision) |
| Pin 3 | RX_DV/MII_MODE — Receive data valid / MII mode strap |
| Pin 4 | RX_ER — Receive error (MII) |
| Pin 5 | RXD0 — Receive data 0 / RMII reference clock |
| Pin 6 | RXD1 — Receive data 1 |
| Pin 7 | RXD2 — Receive data 2 (MII only) |
| Pin 8 | RXD3 — Receive data 3 (MII only) |
| Pin 9 | TX_CLK — Transmit clock / RMII clock (strap dependent) |
| Pin 10 | TX_EN — Transmit enable |
| Pin 11 | TXD0 — Transmit data 0 |
| Pin 12 | TXD1 — Transmit data 1 |
| Pin 13 | TXD2 — Transmit data 2 (MII only) |
| Pin 14 | TXD3 — Transmit data 3 (MII only) |
| Pin 15 | CRS_DV — Carrier sense / receive data valid (MII) |
| Pin 16 | COL — Collision detect (MII) |
| Pin 17 | MDC — Management data clock |
| Pin 18 | MDIO — Management data I/O |
| Pin 19 | INT — Interrupt output |
| Pin 20 | RESET_n — Hardware reset (active low) |
| Pin 21 | LED0 — Link/activity LED |
| Pin 22 | LED1 — Speed/status LED |
| Pin 23 | TX_P — MDI differential transmit, positive |
| Pin 24 | TX_N — MDI differential transmit, negative |
| Pin 25 | RX_P — MDI differential receive, positive |
| Pin 26 | RX_N — MDI differential receive, negative |
| Pin 27 | VDDIO — Digital I/O supply (1.8/2.5/3.3 V strap-dependent) |
| Pin 28 | VDD — Digital core supply |
| Pin 29 | GND — Ground |
| Pin 30 | GND — Ground |
| Pin 31 | NC — Not connected (per datasheet) |
| Pin 32 | NC — Not connected (per datasheet) |
Typical Applications
DP83826AI is suitable for 7 applications: EtherCAT Slave Modules, Profinet IRT Devices, Industrial Servo Drives, Distributed I/O Stations, Small-Form-Factor PLCs and Edge Controllers, Substation Automation (IEC 61850) IEDs, Industrial Network Sensors and Encoders.
EtherCAT Slave Modules
The DP83826AI's deterministic sub-microsecond loop latency in 100 Mbps full-duplex mode makes it purpose-built for EtherCAT slave nodes, where the PHY's bounded transmit/receive pipeline delay directly determines whether the slave meets the distributed-clock jitter budget for synchronized motion. Placed between the EtherCAT slave controller (ESC, such as TI's LAUNCH-ETHERCAT or an FPGA implementing ET1100) and the isolation transformer, it converts MII/RMII MAC data into 100BASE-TX MLT-3 signaling on the MDI pair while preserving sub-microsecond timing. The improved EMC margin relative to DP83826I is a real advantage in factory cabinets with switching VFDs nearby. Designers should size transformer center-tap capacitance and use a 50 MHz reference clock for RMII mode to maintain the latency specification.
Recommended
Profinet IRT Devices
Profinet IRT (Isochronous Real-Time) class 3 demands bounded end-to-end latency through the PHY, which is exactly what the DP83826AI's deterministic-latency design targets. In an IRT switch port or IO device, the PHY is connected to the host's MAC running a Profinet IO stack, with the MAC interface selected via straps as MII for full 4-bit-wide bus, or RMII when pin counts are limited. The industrial -40 to +85 C rating allows cabinet-installed Profinet devices without thermal derating. Cable diagnostics assist commissioning engineers in locating wiring faults and pair swaps typical of installed industrial cabling.
Recommended
Industrial Servo Drives
In a digital servo drive, the DP83826AI delivers the deterministic physical-layer connection to an EtherCAT or Profinet IRT master controlling multi-axis coordinated motion, where PHY latency variation would translate directly into axis-following error. The 32-VQFN (RHB) 5x5 mm package with exposed thermal pad dissipates adequately inside a drive enclosure sharing a backplane with IGBT power stages. The improved EMC performance against DP83826I is helpful given the high dV/dt noise typical of servo inverter switching. Pair with isolated RS-485 and CAN-FD transceivers on the low-speed side of the drive MCU for a complete fieldbus interface.
Recommended
Distributed I/O Stations
Distributed I/O stations sit on the factory Ethernet spine and expose digital and analog channel data to a controller over EtherCAT or Profinet. The DP83826AI's small 5x5 mm VQFN footprint enables the compact IO backplane mechanics typical of a 16- or 32-channel fieldbus slice. Its cable diagnostics exposed via MDIO let the IO station self-report MDI pair faults back to the controller, reducing mean-time-to-repair on installed systems. The deterministic receive path is also useful for timestamp propagation that some higher-layer industrial protocols piggyback on the physical-layer sync.
Recommended
Small-Form-Factor PLCs and Edge Controllers
A 32-VQFN 10/100 Ethernet PHY with industrial temperature is a good fit for compact PLCs and edge controllers that expose EtherCAT or Modbus-TCP/IP port counts while sharing board real estate with digital I/O. The DP83826AI's industrial-grade ESD margin (Class A at 8 kV contact per IEC 61000-4-2) avoids system-level ESD retrofit and lets the same design pass factory-acceptance testing on the first build. RMII mode frees up several MAC-side pins for local IO instead of full MII bus width. Strap-set PHY address lets multiple PHYs or a future PHY + switch coexistence coexist on the MDIO bus.
Recommended
Substation Automation (IEC 61850) IEDs
Intelligent Electronic Devices (IEDs) used in electrical substations communicate via IEC 61850 over a process bus, where layer-2 switching must preserve sample-value synchronization aligned to IEEE 1588. The DP83826AI's deterministic receive path supports IEEE 1588 timestamp propagation within its declared accuracy budget. The industrial temperature and IEC 61000-4-2 enhanced ESD margin on the 'A' revision matters for utility-gear installation environments. Substation engineers typically follow IEC 61850-3 / IEEE 1613 environmental specs, which a PHY alone does not meet but which its component-level margin helps the complete system achieve.
Recommended
Industrial Network Sensors and Encoders
Industrial encoders, inclinometers, and force sensors increasingly expose EtherCAT or Profinet, replacing traditional 4-20 mA signaling. A 10/100 PHY like the DP83826AI in a 5x5 mm VQFN fits inside the sensor housing and saves PCB space for the sensor frontend and MCU. The PHY's low power consumption is important because sensor nodes are often powered from a single twisted pair via PoE-lite or from a small DC bus. Cable diagnostics help field technicians diagnose which sensor in a multi-drop EtherCAT segment has a wiring fault, reducing commissioning time.
Recommended
Recommended Products Summary
Engineering reference data for DP83826AI — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DP83826I | DP83826AIRHBR | DP83848 |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 32-VQFN (RHB) 5x5 mm | 32-VQFN (RHB) 5x5 mm - same | 32-VQFN (RHB) 5x5 mm - same | 32-VQFN (RHB) 5x5 mm - same |
| Product Type | Industrial 10/100 Ethernet PHY (deterministic, EtherCAT-optimized) | Industrial 10/100 Ethernet PHY (deterministic, EtherCAT-optimized) | Same die as DP83826AI, tape-and-reel reel variant | General-purpose 10/100 Ethernet PHY |
| MAC Interface | MII / RMII | MII / RMII | MII / RMII | MII / RMII |
| Operating Temperature | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) | 0 C to +70 C (commercial, ext variants available) |
| Deterministic Latency for EtherCAT | Yes (binned/specified) | Yes | Yes (same die) | No |
| Cable Diagnostics (TDR) | Yes | Yes | Yes (same die) | Limited (link-quality monitor only) |
| RX_CLK Strap (Link-Drop Prevention) | Yes (added on 'A' revision) | No | Yes (same die) | No |
| Lifecycle Status | Active | Active (legacy industrial) | Active (reel variant) | Active (mature) |
Key Differentiators
- Enhanced IEC 61000-4-2 Class A 8 kV ESD margin (vs DP83826I)
- RX_CLK strap option for link-drop prevention (vs DP83826I)
- Targeted EtherCAT deterministic-latency characterization (vs DP83848)
Design Notes
Route the MDI differential pairs (TX_P/TX_N and RX_P/RX_N) as a 100-ohm differential microstrip, length-matched to within 2 mm, with no stubs and no via transitions if possible. Place the 1:1 isolation transformer within 25 mm of the MDI pins, and provide a continuous analog ground reference plane under the MDI traces. Decouple each supply pin with a 100 nF X7R capacitor within 2 mm, plus a bulk 10 uF tantalum near the analog supply pin to suppress switching noise from the MAC-side VDDIO bus. The DP83826AI's improved EMC margin over DP83826I requires careful magnetics selection (integrated common-mode choke) to realize the full Class A margin; using a no-CM-choke transformer will not defeat ESD immunity but will degrade radiated-emissions margin.
Do not strap the PHY for MII mode while routing the MAC bus as RMII, and vice versa - mismatch leaves the link permanently down and can prevent the MDIO identify cycle. Do not omit the reset RC delay (typically a 10 kohm pull-up to 3.3 V with a 1 nF to GND) at the RESET_n pin; without it, the PHY may boot before the MAC is ready and reject valid frames. Avoid 25 MHz + 125 MHz reference-clock modes that the DP83826A family does not support - it requires either 25 MHz (RMII 50 MHz synthesized internally) or 50 MHz direct, depending on strap. Estimated: typical reset RC time constant is 10 kohm * 1 nF = 10 us, well below the 100 ms MAC boot window.
To preserve the DP83826AI's improved IEC 61000-4-2 Class A 8 kV margin, use a transformer with integrated common-mode choke on the MDI side, and place an 0805-sized TVS array (e.g., SP3010 or PESD5V0L4UG) right at the RJ-45 magnetic secondary. If your enclosure is plastic and exposed to human-touch ESD, add a spark-gap or steering-diode array on the chassis ground path. For PLC- or VFD-cabinet installations, place a ferrite bead on each MDI trace near the connector to limit common-mode current flow, and bond the PCB ground to chassis ground with a low-impedance flat strap, not a single wire.
Pin 32 of the 32-VQFN package is the exposed thermal pad - stitch it to the inner-ground plane with a 4x4 via array for thermal relief at 100 mA continuous draw. Keep all strap configuration pins accessible for factory rework; pulling them high vs. low selects MII/RMII, PHY address, master/slave, and 10/100. The MDIO pull-up to 3.3 V must be present (typically 4.7 kohm) on every DP83826AI design because the PHY does not provide internal pull-up - missing MDIO pull-up makes the PHY unreachable for management reads.
Compliance Information
Industrial temperature grade -40 to +85 C; not AEC-Q100 (this is an industrial Ethernet PHY, not automotive). Enhanced ESD performance rated to 8 kV contact (IEC 61000-4-2) with Class A margin per TI E2E forum thread on DP83826A vs DP83826I. RoHS and lead-free compliance per TI product page; for REACH/halogen detailed disclosures, see TI's product-compliance portal.
