DS90LV001TMX/NOPB - 800 Mbps LVDS Buffer | Texas Instruments
MPN: DS90LV001TMX/NOPB ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3.02 | $3.02 |
| 10 | $2.71 | $27.10 |
| 100 | $2.42 | $242.00 |
| 500 | $2.16 | $1,080.00 |
| 1,000 | $1.92 | $1,920.00 |
| 2,500 | $1.74 | $4,350.00 |
DS90LV001TMX/NOPB Overview
An LVDS buffer (Low-Voltage Differential Signaling buffer / re-driver) is a type of high-speed differential interface IC that regenerates and re-shapes a weak or distorted differential signal so it can drive another transmission line segment. In the broader system hierarchy it sits under interface ICs, then signal-conditioning devices, and ultimately under wired-connectivity semiconductors. LVDS buffers are essential building blocks in any system where the original LVDS transmitter cannot source enough current to reach a distant receiver while still meeting the TIA/EIA-644 eye-diagram mask.
Key features of the DS90LV001TMX/NOPB include a 2.0 ns typical propagation delay, low jitter and low skew design that holds the differential output within tight limits, integrated 100 ohm input termination across the LVDS input pair, and an LVDS output stage that supports both point-to-point and multi-drop topologies. The device is designed to accept LVPECL inputs when AC-coupled, giving it cross-standard compatibility within the same SOIC-8 footprint. A single channel is provided per package, and the part is pin-to-pin compatible with the rest of the DS90LV001 family.
Architecturally, the DS90LV001 uses a current-mode LVDS driver with on-chip bias generation. The differential receiver detects the incoming signal and re-times it through an internal logic stage that drives the output current-steering network. Because the part is a transparent buffer, it does not add protocol encoding or clock-data recovery - it simply regenerates the differential edge, restoring amplitude and common-mode level so the signal can traverse another cable, connector, or FR-4 stub.
Typical applications for the DS90LV001TMX/NOPB include clock distribution across backplanes, buffering LVDS links between mezzanine cards, extending FR-4 trace runs in telecom and networking line cards, cable driving in point-to-point LVDS links, and acting as a stub-length isolator in large distributed systems where the unterminated stub length would otherwise limit the maximum achievable data rate. Designers also use it as a fan-out repeater when one LVDS source must drive two downstream loads.
A key design consideration is the placement of external AC-coupling capacitors when LVPECL sources must be interfaced - these capacitors must be placed close to the device inputs to control the common-mode voltage. The DS90LV001's 8-pin SOIC footprint keeps the layout small but thermal performance is modest, so for applications that require higher output drive or multi-channel operation a higher-current or multi-channel LVDS part from the same family should be considered. This page synthesizes distributor stock, drop-in SOIC-8 alternatives, and practical PCB-layout notes not found in the manufacturer datasheet.
Drop-in alternatives for DS90LV001TMX/NOPB — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DS90LV001TM/NOPB
✅ Drop-In📋 Reference alternative (not in catalog)
DS90LV001TLD/NOPB
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
SN65LVDS1DBVR
✅ Drop-In📋 Reference alternative (not in catalog)
SN65LVDS2DBVR
✅ Drop-In📋 Reference alternative (not in catalog)
DS90LV004TVS/NOPB
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DS90LV001TMX/NOPB Specifications
| Function | LVDS-to-LVDS Buffer / Re-driver |
| Number of Channels | 1 |
| Input Protocol | LVDS, LVPECL (AC-coupled) |
| Output Protocol | LVDS |
| Maximum Signaling Rate | 800 Mbps |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (typical 3.3 V) |
| Supply Current | 70 mA (typical) |
| Propagation Delay | 2.0 ns (typical) |
| Differential Input Threshold | ±100 mV (LVDS compliant) |
| Input Termination | 100 ohm integrated |
| Operating Temperature Range | -40 C to +85 C |
| Package | 8-pin SOIC (D), 3.90 mm body width |
| Mounting Type | Surface Mount |
| MSL Level | MSL1 (per JEDEC J-STD-020) |
| Lead-Free / RoHS | Yes (NOPB suffix = lead-free, RoHS compliant) |
| Packaging | Tape and Reel (TMX suffix) |
DS90LV001TMX/NOPB Pin Configuration
| Pin 1 | IN+ — Non-inverting LVDS input (with on-chip 100 ohm differential termination to IN-) |
| Pin 2 | IN- — Inverting LVDS input (with on-chip 100 ohm differential termination to IN+) |
| Pin 3 | VCC — Power supply (3.3 V nominal) |
| Pin 4 | GND — Ground |
| Pin 5 | OUT- — Inverting LVDS output |
| Pin 6 | OUT+ — Non-inverting LVDS output |
| Pin 7 | GND — Ground (must be connected for low-inductance return) |
| Pin 8 | VCC — Power supply (3.3 V nominal) |
Typical Applications
DS90LV001TMX/NOPB is suitable for 7 applications: Backplane Clock Distribution, LVDS Link Extension / Cable Equalization, Telecom / Networking Line Card Buffering, Industrial Imaging / Camera Link Interface, Point-to-Point LVDS Cable Driving, LVPECL-to-LVDS Level Translation (AC-Coupled), Test & Measurement Instrumentation Backplane.
Backplane Clock Distribution
The DS90LV001TMX/NOPB fits backplane clock distribution because its transparent LVDS buffer architecture preserves edge rate and adds only 2.0 ns typical propagation delay, well below one UI at clock frequencies up to 100 MHz. The integrated 100 ohm LVDS input termination eliminates external resistor networks and minimizes stub reflections on the backplane, and the 3.0-3.6 V single-rail supply matches common backplane rail voltages. Designers can fan out one LVDS clock source to multiple cards through a tree of DS90LV001 buffers while controlling cumulative timing skew. According to TI datasheet, the device supports clock distribution topologies common in telecom and datacom backplanes.
Recommended
LVDS Link Extension / Cable Equalization
The DS90LV001TMX/NOPB is a strong fit for LVDS link extension because it re-shapes and re-transmits a degraded differential signal so the link can be extended across longer cables, connectors, or FR-4 trace runs. With 800 Mbps of headroom and a typical propagation delay of 2.0 ns, the buffer allows a system to exceed the original transmitter's drive reach without altering the protocol. Designers place one or more DS90LV001 buffers inline to bridge long backplane segments or external cable assemblies, restoring amplitude and common-mode level. The SOIC-8 footprint makes it easy to insert the buffer at any mid-link access point.
Recommended
Telecom / Networking Line Card Buffering
The DS90LV001TMX/NOPB is well suited to telecom and networking line-card buffering because it operates from a single 3.3 V rail at 70 mA, simplifying power tree design, and is qualified across the -40 C to +85 C industrial temperature range. Its 800 Mbps capability covers the data rates commonly used in LVDS-based control planes, serializer/deserializer (SerDes) interfaces, and inter-card control links. The device's 100 ohm integrated termination matches standard LVDS media directly, and the SOIC-8 package is small enough for dense line-card layouts. The buffer's low jitter preserves signal integrity across the backplane.
Recommended
Industrial Imaging / Camera Link Interface
The DS90LV001TMX/NOPB fits camera-link and industrial imaging interfaces because it provides 800 Mbps of LVDS bandwidth, sufficient for channel-link LVDS-based camera data and control signals. The device's transparent buffering allows designers to place the camera connector at a distance from the FPGA/ASIC receiver while still meeting the LVDS eye mask. The 100 ohm integrated termination matches channel-flat cable characteristic impedance directly, reducing stub-induced reflections on long flat-flex assemblies. Designers frequently use the DS90LV001 as a repeater between flat-flex cable assemblies and the main PCB.
Recommended
Point-to-Point LVDS Cable Driving
The DS90LV001TMX/NOPB is a strong choice for point-to-point LVDS cable driving because its LVDS output stage can drive twisted-pair or differential cable assemblies directly while its 100 ohm input termination matches the cable characteristic impedance. The 3.0-3.6 V supply and 70 mA consumption keep power dissipation modest, important when many buffered links share a single rail. The buffer allows system designers to extend the LVDS link well beyond the original transmitter's native drive reach, with the 800 Mbps capability headroom sufficient for most industrial control and instrumentation applications.
Recommended
LVPECL-to-LVDS Level Translation (AC-Coupled)
The DS90LV001TMX/NOPB can serve as an LVPECL-to-LVDS level translator when its LVDS inputs are AC-coupled, with external biasing networks setting the input common-mode voltage. This allows system designers to interface legacy LVPECL clock sources to LVDS receivers without a dedicated translator IC. The device's transparent buffering preserves edge rate and timing integrity, while the SOIC-8 footprint keeps the translator footprint small. According to TI datasheet, the input stage accepts LVPECL signals when AC-coupled, giving the DS90LV001 cross-standard compatibility within a single footprint.
Recommended
Test & Measurement Instrumentation Backplane
The DS90LV001TMX/NOPB fits test-and-measurement backplane applications because it offers 800 Mbps of bandwidth with low jitter and 2.0 ns propagation delay, well-suited to clock and trigger distribution in modular instruments. The device's transparent buffering allows arbitrary topologies (point-to-point, multi-drop, fan-out) without protocol encoding, and the 3.3 V supply aligns with typical instrument-rail voltages. Designers frequently cascade multiple DS90LV001 buffers to fan out a master clock to many instrument modules. The SOIC-8 footprint keeps the buffer footprint compatible with standard instrument backplane layouts.
Recommended
Recommended Products Summary
Engineering reference data for DS90LV001TMX/NOPB — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DS90LV001TM/NOPB | DS90LV001TLD/NOPB | SN65LVDS1DBVR | DS90LV004TVS/NOPB |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 8-SOIC (D) | 8-SOIC (D) | 8-WSON (NGK) | SOT-23-5 | 48-TQFP (PHP) |
| Function | LVDS Buffer / Re-driver | LVDS Buffer / Re-driver | LVDS Buffer / Re-driver | LVDS Line Driver | LVDS 4-Channel Buffer |
| Max Data Rate | 800 Mbps | 800 Mbps | 800 Mbps | 400 Mbps typical | 1500 Mbps per channel |
| Number of Channels | 1 | 1 | 1 | 1 driver | 4 |
| Supply Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 2.4 V to 3.6 V | 3.0 V to 3.6 V |
| Propagation Delay | 2.0 ns (typical) | 2.0 ns (typical) | 2.0 ns (typical) | 1.7 ns (typical) | 1.6 ns (typical) |
| Integrated Input Termination | 100 ohm differential | 100 ohm differential | 100 ohm differential | External required | 100 ohm differential |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| RoHS / Lead-Free | Yes (NOPB) | Yes (NOPB) | Yes (NOPB) | Yes | Yes (NOPB) |
Key Differentiators
- Integrated 100 ohm LVDS input termination (vs SN65LVDS1DBVR)
- Single-rail 3.3 V supply (no separate VCCO) (vs LVPECL buffers (e.g., SY89829L))
- Transparent buffer with no protocol encoding (vs SN65LVDS1DBVR)
- SOIC-8 package availability with exposed thermal pad option (WSON-8) (vs Discrete LVDS re-driver implementations)
Design Notes
Place a 0.1 uF ceramic decoupling capacitor as close as possible to each VCC pin (pins 3 and 8) and connect both GND pins (4 and 7) to a low-impedance ground plane. Use a continuous ground plane under the device to provide a low-inductance return path for the high-speed differential signals. For multi-layer boards, place the LVDS traces on a layer adjacent to the ground plane with controlled 100 ohm differential impedance. Keep LVDS traces short and avoid right-angle bends; use 45-degree bends or curved traces to minimize reflections.
Maintain 100 ohm differential impedance on the LVDS traces, using either microstrip or stripline geometry. The integrated 100 ohm input termination eliminates the need for external resistor networks but still requires the PCB trace impedance to match the termination. For LVPECL-to-LVDS translation, place the AC-coupling capacitors (typically 0.1 uF) as close as possible to the IN+ and IN- pins and add biasing networks to set the LVDS input common-mode voltage. Keep LVDS pairs tightly coupled with constant spacing to reject common-mode noise.
The DS90LV001 in SOIC-8 (D) package dissipates approximately 70 mA x 3.3 V = 231 mW under typical operation, which is well within the SOIC-8 thermal envelope. For most applications, no heatsink is required. However, when the device is cascaded in multi-buffer clock trees, the cumulative power dissipation should be checked against the system thermal design. The WSON-8 (NGK) variant (DS90LV001TLD/NOPB) provides a lower thermal resistance through its exposed thermal pad and is recommended when stacking multiple buffers on a small board area.
Do not leave either VCC or GND pin disconnected - both VCC pins (3 and 8) and both GND pins (4 and 7) must be connected for proper operation. Do not exceed the absolute maximum rating of 4 V on VCC or expose inputs to ESD levels beyond the HBM rating without protection. When cascading multiple DS90LV001 buffers, budget the cumulative 2.0 ns propagation delay against the system timing budget - each buffer adds delay. For LVPECL inputs, AC-coupling capacitors and biasing networks are required; do not attempt DC-coupling without proper level shifting.
Compliance Information
NOPB suffix indicates lead-free, RoHS-compliant per TI product page. AEC-Q100 not applicable (industrial-grade, not automotive). REACH compliance per TI material declaration.
