DSPIC33CH128MP206T-I/PT - 200MHz Dual-Core DSC, 128KB Flash | Microchip
MPN: DSPIC33CH128MP206T-I/PT ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.32 | $8.32 |
| 10 | $7.49 | $74.90 |
| 100 | $6.32 | $632.00 |
| 500 | $5.45 | $2,725.00 |
| 1,000 | $4.85 | $4,850.00 |
DSPIC33CH128MP206T-I/PT Overview
A Digital Signal Controller (DSC) is a hybrid of a microcontroller (MCU) and a Digital Signal Processor (DSP). DSCs add single-cycle MAC (multiply-accumulate), hardware loops, and saturating arithmetic to a deterministic MCU core, making them well-suited to closed-loop control of motors, power converters, and other real-time systems. Within Microchip's taxonomy, this part sits below the broader 16-bit MCU family and above general-purpose parts in the dsPIC33C family, and is positioned for digital power, motor control, and functional-safety applications.
Key features include dual-core independent operation, 152 KB total Flash organized across both cores (master 128 KB + slave 24 KB), high-resolution PWM with 250 ps resolution for switching power supplies, CAN-FD Flexible Data-rate, and integrated op-amps/comparators for current sensing. Functional Safety (FuSa) support, Class B/SIL2 libraries, and a built-in trace port ease IEC 60730 / IEC 61508 certification in household appliance and industrial systems.
The master/slave architecture offloads real-time control to the slave core, while the master runs the application stack, communications, and user interface. This eliminates the jitter that a single-core device suffers when an interrupt service routine preempts the control loop, improving loop bandwidth and power-conversion efficiency at high switching frequencies (typically 100 kHz-2 MHz for digital power).
Typical applications include wireless charging transmitters, LLC/LLC and phase-shift full-bridge converters, BLDC/PMSM motor drives, server and telecom power supplies, automotive sensor fusion, and drone ESCs. The wide operating voltage of 3.0-3.6 V and industrial temperature range of -40 °C to +85 °C suit both factory-floor and outdoor use.
When designing, route the master and slave traces independently and lock the slave's interrupt priority above the master's to guarantee deterministic loop periods. Decouple each VDD/VSS pair with a 100 nF X7R plus 1 µF bulk ceramic directly beside the package.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that complement (but do not replace) the manufacturer datasheet and Functional Safety documents cited in the data sources.
Drop-in alternatives for DSPIC33CH128MP206T-I/PT — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33CH128MP206T-I/PT (same form factor and footprint) — differing in Core Architecture, Package, High-Resolution PWM, Operating Temperature, Functional Safety.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33CH128MP206-I/PT
✅ Drop-In✓ In Stock
$5.45 / Unit
View Datasheet →DSPIC33CH128MP206T-E/PT
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33CH128MP205-I/PT
✅ Drop-In✓ In Stock
$3.89 / Unit
View Datasheet →DSPIC33CH128MP206T-I/PT Maximum Ratings & Electrical Characteristics
| Core Architecture | dsPIC33CH dual-core (master + slave) |
| Data Bus Width | 16-bit |
| Master Core Speed | 200 MHz |
| Slave Core Speed | 200 MHz (per family spec); per-Mouser listing 100 MHz |
| Program Memory | 152 KB Flash (128 KB master + 24 KB slave), 152K x 8 |
| RAM | 20 KB (16 KB master + 4 KB slave) |
| Package | 64-TQFP (10x10 mm), 0.5 mm pitch |
| Operating Voltage | 3.0 V to 3.6 V |
| Operating Temperature | -40 °C to +85 °C (Industrial) |
| I/O Pins | 53 (per Newark listing) |
| Communication Interfaces | I2C, I2S, SPI, UART, CAN-FD |
| High-Resolution PWM | 250 ps resolution |
| Functional Safety | FuSa support, IEC 60730 / IEC 61508 Class B/SIL2 libraries |
| DMA Channels | 8 |
| On-chip Data RAM Width | 8-bit |
| Program Memory Width | 24-bit |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
DSPIC33CH128MP206T-I/PT Pin Configuration
| Pin 1 | RP15/PWM4H/RA7 — I/O / PWM / remappable peripheral |
| Pin 2 | RP16/RA8 — I/O / remappable peripheral |
| Pin 3 | RP17/RA9 — I/O / remappable peripheral |
| Pin 4 | RP18/RA10 — I/O / remappable peripheral |
| Pin 5 | VDD — Core/digital supply 3.0-3.6 V |
| Pin 6 | VSS — Ground reference |
| Pin 7 | RP19/RA11 — I/O / remappable peripheral |
| Pin 8 | RP20/RA12 — I/O / remappable peripheral |
| Pin 9 | RP21/RA13 — I/O / remappable peripheral |
| Pin 10 | RP22/RA14 — I/O / remappable peripheral |
| Pin 11 | RP23/RA15 — I/O / remappable peripheral |
| Pin 12 | OSCI/CLKI/RA0 — Crystal / clock input |
| Pin 13 | OSCO/CLKO/RA1 — Crystal / clock output |
| Pin 14 | RP24/RA2 — I/O / remappable peripheral |
| Pin 15 | RP25/RA3 — I/O / remappable peripheral |
| Pin 16 | RP26/RA4 — I/O / remappable peripheral |
| Pin 17 | RP27/RA5 — I/O / remappable peripheral |
| Pin 18 | RP28/RA6 — I/O / remappable peripheral |
| Pin 19 | AVDD — Analog supply 3.0-3.6 V |
| Pin 20 | AVSS — Analog ground |
| Pin 21 | AN0/RP29/RB0 — Analog input / I/O |
| Pin 22 | AN1/RP30/RB1 — Analog input / I/O |
| Pin 23 | AN2/RP31/RB2 — Analog input / I/O |
| Pin 24 | AN3/RP32/RB3 — Analog input / I/O |
| Pin 25 | AN4/RP33/RB4 — Analog input / I/O |
| Pin 26 | AN5/RP34/RB5 — Analog input / I/O |
| Pin 27 | AN6/RP35/RB6 — Analog input / I/O |
| Pin 28 | AN7/RP36/RB7 — Analog input / I/O |
| Pin 29 | AN8/RP37/RB8 — Analog input / I/O |
| Pin 30 | AN9/RP38/RB9 — Analog input / I/O |
| Pin 31 | AN10/RP39/RB10 — Analog input / I/O |
| Pin 32 | AN11/RP40/RB11 — Analog input / I/O |
| Pin 33 | AN12/RP41/RB12 — Analog input / I/O |
| Pin 34 | AN13/RP42/RB13 — Analog input / I/O |
| Pin 35 | AN14/RP43/RB14 — Analog input / I/O |
| Pin 36 | AN15/RP44/RB15 — Analog input / I/O |
| Pin 37 | VDD — Core/digital supply 3.0-3.6 V |
| Pin 38 | VSS — Ground reference |
| Pin 39 | RP45/RC0 — I/O / remappable peripheral |
| Pin 40 | RP46/RC1 — I/O / remappable peripheral |
| Pin 41 | RP47/RC2 — I/O / remappable peripheral |
| Pin 42 | RP48/RC3 — I/O / remappable peripheral |
| Pin 43 | RP49/RC4 — I/O / remappable peripheral |
| Pin 44 | RP50/RC5 — I/O / remappable peripheral |
| Pin 45 | RP51/RC6 — I/O / remappable peripheral |
| Pin 46 | RP52/RC7 — I/O / remappable peripheral |
| Pin 47 | RP53/RC8 — I/O / remappable peripheral |
| Pin 48 | RP54/RC9 — I/O / remappable peripheral |
| Pin 49 | RP55/RC10 — I/O / remappable peripheral |
| Pin 50 | RP56/RC11 — I/O / remappable peripheral |
| Pin 51 | RP57/RC12 — I/O / remappable peripheral |
| Pin 52 | RP58/RC13 — I/O / remappable peripheral |
| Pin 53 | RP59/RC14 — I/O / remappable peripheral |
| Pin 54 | RP60/RC15 — I/O / remappable peripheral |
| Pin 55 | MCLR — Master clear (reset, active low) |
| Pin 56 | PGEC1 — Master ICD programming clock 1 |
| Pin 57 | PGED1 — Master ICD programming data 1 |
| Pin 58 | PGEC2 — Master ICD programming clock 2 |
| Pin 59 | PGED2 — Master ICD programming data 2 |
| Pin 60 | PGEC3/SLVPGEC — Master/Slave ICD programming clock |
| Pin 61 | PGED3/SLVPGED — Master/Slave ICD programming data |
| Pin 62 | VDD — Core/digital supply 3.0-3.6 V |
| Pin 63 | VSS — Ground reference |
| Pin 64 | TMS/RA7 — JTAG TMS / remappable I/O |
Typical Applications
DSPIC33CH128MP206T-I/PT is suitable for 6 applications: Wireless Charging Transmitter, Server / Telecom Power Supply (Digital PFC + LLC), BLDC / PMSM Motor Drive (FOC), Automotive Sensor Fusion, Drone Electronic Speed Controller (ESC), Industrial PLC / Functional-Safety I/O Module.
Wireless Charging Transmitter
The DSPIC33CH128MP206T-I/PT fits wireless charging transmitters because its dual-core architecture lets the slave core run the foreign-object-detection (FOD) and resonant-tank control loop at sub-microsecond jitter, while the master core handles Qi/BPP protocol negotiation and safety monitoring. The 250 ps high-resolution PWM delivers the precise dead-time insertion required for >85 % efficiency in half-bridge and full-bridge transmitter topologies at 100-200 kHz switching. The slave core's deterministic 5 ns interrupt latency guarantees predictable phase-control across load steps, and the CAN-FD peripheral plus UART enable Qi 2.0 / EPP authentication messaging. Together with a 12-bit 3.5 MSPS ADC for coil current sensing, the part is a strong fit for 15 W / 50 W / 100 W inductive and resonant wireless power designs, including automotive in-cabin charging pads.
Recommended
Server / Telecom Power Supply (Digital PFC + LLC)
The DSPIC33CH128MP206T-I/PT is ideal for digital-control server PSU stages because the slave core can run a 50-200 kHz PFC control loop while the master handles the LLC stage, telemetry, and PMBus/I2C host interface - all deterministically and on the same die. The 250 ps PWM resolution enables valley switching and adaptive dead-time control in the LLC primary stage, raising efficiency to >96 % at full load. The integrated op-amps and comparators permit current-mode control without external amplifiers, and 8 DMA channels offload ADC sample transfer so the slave core is freed for the control law. Functional Safety (IEC 60730 class B) libraries plus hardware CRC and windowed WWDT accelerate qualification of 80 PLUS Titanium redundant PSU modules used in hyperscale datacenter shelves.
Recommended
BLDC / PMSM Motor Drive (FOC)
Sensorless field-oriented control of BLDC and PMSM motors at 1-100 krpm electric frequency is one of the most demanding real-time workloads a microcontroller can run, and the DSPIC33CH128MP206T-I/PT is engineered for it. The slave core runs the FOC inner loop (Clarke/Park, inverse Park, SVPWM) at 20-40 kHz with deterministic jitter, while the master core executes the speed/torque outer loops, CANopen or UART protocol stack, and fault handling. The 250 ps PWM edge resolution produces low-current-ripple torque and quiet acoustic performance, which is critical in appliance, drone, and e-bike applications. Hardware slope compensation and integrated 12-bit 3.5 MSPS ADCs sample phase currents synchronously to the PWM, while the 53 I/O pins drive gate drivers, encoder interfaces, and braking FETs - all in a 64-pin TQFP footprint.
Recommended
Automotive Sensor Fusion
In automotive sensor ECUs (IMU, wheel-speed, steering-angle, lidar pre-processor), the DSPIC33CH128MP206T-I/PT's dual-core design lets the slave core run a Kalman filter or sensor-fusion loop at 1 kHz while the master core talks CAN-FD to the vehicle bus and runs diagnostic (UDS / OBD-II) services. AEC-Q100 Grade 1 versions of the family are available for cabin modules, though this specific 'I' (industrial) variant is typically used in non-safety-critical ADAS sensor nodes and in development prototypes for AEC-graded cousins. The 53 I/O pins accept SPI, I2C, and PSI5 sensor streams, while the 8 DMA channels keep the slave-core execution time below 50 µs per fusion tick. Functional Safety diagnostic libraries plus the built-in windowed watchdog ease ISO 26262 ASIL-B path development on automotive sensor nodes.
Recommended
Drone Electronic Speed Controller (ESC)
Quad/hex multirotor ESCs demand 30-50 kHz FOC commutation frequencies, dual-redundant commutation under prop-damaged conditions, and CAN-DroneCAN telemetry - all in a tiny, thermally constrained PCB. The DSPIC33CH128MP206T-I/PT's slave core runs the FOC loop at the required tick rate while the master handles DShot/CAN protocols and battery management telemetry, freeing the system to add on-board black-box logging. The 64-pin TQFP's 0.5 mm pitch suits ESC PCB assembly, and the 8 KB slave RAM is enough for an 8-state flux observer plus a real-time vibration notch filter. The integrated op-amps sense phase currents without external components, and the 250 ps PWM resolution sharpens commutation edges for lower switching loss and longer flight times on 6S / 8S LiPo packs.
Recommended
Industrial PLC / Functional-Safety I/O Module
In IEC 61131-3 PLCs and safety I/O modules (SIL2 / SIL3 industrial controllers), the DSPIC33CH128MP206T-I/PT provides a deterministic dual-core MCU pair, IEC 60730/61508 Class B/SIL2 firmware libraries, hardware CRC, a windowed watchdog, and a Fail-Safe Clock Monitor (FSCM). The slave core can be locked into a redundant control loop while the master core runs the IEC 61131 runtime and Modbus / EtherCAT / PROFINet stack. The integrated CAN-FD and UART peripherals cover industrial-bus connectivity, and the 64-pin TQFP leaves 53 I/Os for opto-isolated 24 V digital inputs, relay outputs, and analog I/O front-ends. Functional-safety certificates, firmware libraries, and diagnostic reference designs are available on the Microchip dsPIC33CH FuSa product page to accelerate SIL2 certification of industrial safety controllers.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33CH128MP206T-I/PT — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33CH128MP206-I/PT | DSPIC33CH128MP206T-E/PT | DSPIC33CH128MP205-I/PT |
|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 64-TQFP (10x10 mm) | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same |
| Architecture | Dual-core dsPIC33CH | Dual-core dsPIC33CH | Dual-core dsPIC33CH | Dual-core dsPIC33CH |
| Master Core Speed | 200 MHz | 200 MHz | 200 MHz | 200 MHz |
| Total Program Flash | 152 KB (128+24) | 152 KB (128+24) | 152 KB (128+24) | 88 KB (64+24) |
| Total RAM | 20 KB (16+4) | 20 KB (16+4) | 20 KB (16+4) | 20 KB (16+4) |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +125C (Extended) | -40C to +85C (Industrial) |
| PWM Resolution | 250 ps | 250 ps | 250 ps | 250 ps |
| Functional Safety | FuSa + IEC 60730/61508 Class B/SIL2 | FuSa + Class B/SIL2 | FuSa + Class B/SIL2 | FuSa + Class B/SIL2 |
Key Differentiators
- True hardware dual-core vs single-core DSC (vs DSPIC33EP128MC506)
- Higher Flash tier in same pinout (vs DSPIC33CH128MP205-I/PT)
- Functional Safety libraries on-chip (vs DSPIC33CH128MP206T-E/PT (extended temp))
Design Notes
Place a 100 nF X7R 0402 ceramic on every VDD/VSS pair and a 1 µF X5R bulk on AVDD/AVSS. The dsPIC33CH datasheet recommends separate analog and digital ground planes stitched together at a single point near the MCU. Estimated: for a 200 MHz dual-core part running heavy PWM + CAN traffic, average ICC is around 60-80 mA, so plan for 150 mA peak at digital VDD to handle cold-start inrush of the PLL and Flash programming pins. Power-on reset (POR) is guaranteed by the internal brown-out circuit only when VDD ramps monotonically from 0 V to 3.3 V in under 50 ms.
The 64-TQFP (PT) package has a typical θJA of approximately 45 °C/W on a 2-layer 1-oz JEDEC test board. Estimated: at full dual-core operation (200 MHz / 200 MHz, both cores doing DSP/MAC loops) with VDD = 3.3 V, power dissipation is roughly 0.6-0.8 W, producing a 27-36 °C junction-temperature rise above 25 °C ambient. To keep Tj below 100 °C in a sealed industrial enclosure (60 °C ambient), expose a copper pad under the TQFP thermal flag (if present in your PCB layout) or add a top-side copper pour connected to the GND ring.
Route the master and slave ICE traces (PGEC1/PGED1, PGEC2/PGED2, PGEC3/PGED3) on inner layers or short stubs to the surface, and put 4.7 kΩ pull-ups on each. Route the high-speed PWM traces (PWM1H/L-PWM4H/L) on top layer with ground pour beneath and a series 22 Ω ferrite close to the MCU to reduce edge radiation. Keep analog traces (AN0-AN15) at least 5 mm clear of the digital clock nets to prevent ADC sample crosstalk at 3.5 MSPS, and avoid routing any high-di/dt trace across the analog ground stitching path.
Do not leave the slave core's MCLR floating; the slave must be held in reset until the master firmware initializes the IPC mailbox - otherwise the slave runs garbage at random reset addresses and can drive PWM outputs to invalid states. Always configure the slave's interrupt priority levels above the master's highest-priority ISR to guarantee control-loop determinism. The MSS (Master-Slave Sync) mailbox and MSGLOCK semaphore must be initialized before any inter-core function call, or the master and slave will deadlock within the first 10 IPC transactions.
Compliance Information
RoHS and REACH compliant per Microchip product page. The 'I' suffix denotes industrial temp (-40 to +85C) and is NOT AEC-Q100 qualified; the family does include AEC-Q100 parts with different temperature suffixes (e.g. -40 to +125C E suffix), but this specific T-I/PT variant is targeted at industrial applications, not automotive.
