DSPIC33CH128MP205-I/PT - 100MHz Dual-Core DSC, 128KB | Microchip
MPN: DSPIC33CH128MP205-I/PT β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6.94 | $6.94 |
| 10 | $6.24 | $62.40 |
| 100 | $5.55 | $555.00 |
| 500 | $5 | $2,500.00 |
| 1,000 | $4.44 | $4,440.00 |
| 3,000 | $3.89 | $11,670.00 |
DSPIC33CH128MP205-I/PT Overview
A Digital Signal Controller (DSC) is a hybrid MCU+DSP class of device β a microcontroller core augmented with a single-cycle hardware multiplier, dual 40-bit accumulators, and DSP-oriented addressing modes. It sits in the hierarchy as: DSC -> 16-bit MCU -> Microcontroller -> Embedded Processor -> Semiconductor. The dsPIC33CH is the first Microchip DSC family to instantiate two dsPIC cores in one package, enabling master-slave architectures where one core offloads real-time control loops to the slave.
Key features include 152 KB total Flash (128 KB master / 24 KB shared), 16 KB SRAM, four 16-bit high-resolution PWM channels with 250 ps resolution, two 12-bit ADC modules running up to 3.5 Msps, four analog comparators, CAN FD, and a Functional Safety (FuSa) companion architecture. The dual-core topology dramatically reduces interrupt latency for time-critical control loops in digital power supply applications.
The device integrates dedicated peripherals for switched-mode power supply (SMPS) control β high-resolution PWM, slope compensation, and current blanking β and pairs this with motor-control PWM, quadrature encoder interfaces, and a Peripheral Trigger Generator (PTG). The slave core communicates with the master through shared RAM and hardware semaphores rather than over a mailbox peripheral.
Typical applications include wireless charging transmitters, server and telecom SMPS digital loops, BLDC / PMSM motor drives (drones, e-bikes, robot vacuum cleaners), and automotive sensors requiring ASIL-B-class functional safety. The FuSa features (lockstep monitor, dual watchdog timers, ECC on Flash/SRAM, hardware BIST) make it suitable for safety-critical applications.
When designing with this device, allocate the slave core to the tightest inner current control loop and the master to housekeeping, communications, and supervisory tasks. Ensure the dual-core mailbox is dimensioned for your worst-case inter-core message rate, and validate thermal rise under peak DSP load since simultaneous dual-core operation at 200 MHz adds measurable dissipation compared to single-core designs.
This page synthesises distributor stock and pricing, verified drop-in variants in the same TQFP-48 footprint, and practical dual-core design notes not found on the manufacturer summary page.
Drop-in alternatives for DSPIC33CH128MP205-I/PT β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33CH128MP205-I/PT (same form factor and footprint) β differing in Core Architecture, Package, High-Resolution PWM, Slave Core Speed, ADC.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
DSPIC33CH128MP205-I/M4
β Drop-Inβ In Stock
$5.48 / Unit
View Datasheet βDSPIC33CH128MP205-E/PT
β Drop-Inπ Reference alternative (not in catalog)
DSPIC33CK128MP205-I/PT
β Drop-Inπ Reference alternative (not in catalog)
DSPIC33CH128MP203-I/PT
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
DSPIC33EP128GS705-I/PT
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
DSPIC33CH128MP205-I/PT Maximum Ratings & Electrical Characteristics
| Core Architecture | Dual-core dsPIC33C (master + slave), 16-bit DSC |
| Max CPU Frequency | 200 MHz per core (180 MHz dual-core mode) |
| Instruction Set | 16-bit dsPIC with DSP extensions |
| Program Flash (Master) | 128 KB |
| PRAM (Slave shared) | 4 KB |
| Total Flash | 152 KB (128 KB master + 24 KB shared) |
| SRAM | 16 KB |
| Operating Voltage | 3.0 V to 3.6 V |
| Operating Temperature | -40 C to +85 C (industrial) |
| Package | TQFP-48 (PT), 7x7 mm |
| High-Resolution PWM | 4 x 16-bit, 250 ps resolution |
| ADC | 2 x 12-bit, up to 3.5 Msps |
| CAN FD | Yes |
| Functional Safety | FuSa features (lockstep, ECC, BIST) |
| Mounting Type | Surface Mount |
| MSL Level | 3 (168 hours) |
| RoHS Status | Compliant |
| DMA Channels | 8 |
DSPIC33CH128MP205-I/PT Pin Configuration
| Pin 1 | RP58/PWM4H/AN18/RB10 β Remappable I/O, PWM4H output, ADC analog input |
| Pin 2 | RP59/PWM4L/CMP2A/AN17/RB11 β Remappable I/O, PWM4L output, comparator input |
| Pin 3 | RP60/PWM3H/AN16/RB12 β Remappable I/O, PWM3H output |
| Pin 4 | RP61/PWM3L/AN15/RB13 β Remappable I/O, PWM3L output |
| Pin 5 | RP62/PWM2H/CMP1A/AN14/RB14 β Remappable I/O, PWM2H output |
| Pin 6 | RP63/PWM2L/AN13/RB15 β Remappable I/O, PWM2L output |
| Pin 7 | RP64/AN12/RB0 β Remappable I/O, ADC analog input |
| Pin 8 | RP65/AN11/RB1 β Remappable I/O, ADC analog input |
| Pin 9 | RP66/AN10/RB2 β Remappable I/O, ADC analog input |
| Pin 10 | RP67/AN9/RB3 β Remappable I/O, ADC analog input |
| Pin 11 | RP68/AN8/RB4 β Remappable I/O, ADC analog input |
| Pin 12 | RP69/PWM1H/AN7/RB5 β Remappable I/O, PWM1H output |
| Pin 13 | RP70/PWM1L/AN6/RB6 β Remappable I/O, PWM1L output |
| Pin 14 | RP52/AN5/RC12 β Remappable I/O, ADC analog input |
| Pin 15 | RP53/AN4/CMP2B/RC13 β Remappable I/O, comparator input |
| Pin 16 | RP54/AN3/CMP1B/RC14 β Remappable I/O, comparator input |
| Pin 17 | RP55/AN2/CMP3A/RC15 β Remappable I/O, comparator input |
| Pin 18 | VDD β Digital supply voltage (3.0 V to 3.6 V) |
| Pin 19 | VSS β Digital ground reference |
| Pin 20 | RP75/SCL1/RC8 β I2C1 clock, remappable I/O |
| Pin 21 | RP76/SDA1/RC9 β I2C1 data, remappable I/O |
| Pin 22 | RP32/PWM1H/RC0 β Remappable I/O, PWM1H alt output |
| Pin 23 | RP33/PWM1L/RC1 β Remappable I/O, PWM1L alt output |
| Pin 24 | RP40/UART1TX/RC2 β UART1 transmit, remappable I/O |
| Pin 25 | RP41/UART1RX/RC3 β UART1 receive, remappable I/O |
| Pin 26 | RP42/SPI1SCK/RC4 β SPI1 clock, remappable I/O |
| Pin 27 | RP43/SPI1SDI/RC5 β SPI1 data in, remappable I/O |
| Pin 28 | RP44/SPI1SDO/RC6 β SPI1 data out, remappable I/O |
| Pin 29 | RP45/CAN1TX/RC7 β CAN FD transmit, remappable I/O |
| Pin 30 | RP46/CAN1RX/RD8 β CAN FD receive, remappable I/O |
| Pin 31 | VDD β Digital supply voltage (3.0 V to 3.6 V) |
| Pin 32 | VSS β Digital ground reference |
| Pin 33 | MCLR β Master clear reset (active low) |
| Pin 34 | OSCI/RC12 β Crystal oscillator input or remappable I/O |
| Pin 35 | OSCO/RC13 β Crystal oscillator output or remappable I/O |
| Pin 36 | SOSCI/RP50/RC14 β Secondary oscillator in |
| Pin 37 | SOSCO/RP51/RC15 β Secondary oscillator out |
| Pin 38 | TDO/RP48/RD3 β JTAG test data out |
| Pin 39 | TDI/RP49/RD4 β JTAG test data in |
| Pin 40 | TMS/RP55/RD5 β JTAG test mode select |
| Pin 41 | TCK/RP56/RD6 β JTAG test clock |
| Pin 42 | AVSS β Analog ground reference |
| Pin 43 | AVDD β Analog supply voltage (3.0 V to 3.6 V) |
| Pin 44 | RP46/AN1/CMP3C/RA0 β Remappable I/O, ADC analog, comparator input |
| Pin 45 | RP47/AN0/CMP3D/RA1 β Remappable I/O, ADC analog, comparator input |
| Pin 46 | RP48/AN2/CMP2C/RA2 β Remappable I/O, comparator input |
| Pin 47 | RP49/AN3/CMP2D/RA3 β Remappable I/O, comparator input |
| Pin 48 | RP50/PGC1/AN4/RA4 β PGC1 ICD clock, debug port, ADC input |
Typical Applications
DSPIC33CH128MP205-I/PT is suitable for 6 applications: Wireless Charging Transmitter Control, Server / Telecom SMPS Digital Loop, BLDC / PMSM Motor Drives (Drones, e-Bikes, Robotics), Automotive Safety Sensors (ASIL-B), Digital LED Lighting Drivers, Industrial AC-DC Front-End PFC.
Wireless Charging Transmitter Control
The DSPIC33CH128MP205-I/PT's dual-core architecture suits Qi and AirFuel wireless charging transmitters where the slave core services the resonant inverter inner control loop (100 kHz to 6.78 MHz) while the master handles Qi protocol state machine, Foreign Object Detection (FOD), and PMBus telemetry. The 250 ps PWM resolution is critical for ZVS/soft-switching timing, and the 3.5 Msps ADC samples tank current synchronously with the PWM cycle for cycle-by-cycle current mode control. Compared to a single-core MCU, the slave core's deterministic response removes the 1-3 microsecond jitter introduced by wireless stack interrupt latencies, increasing coil-to-coil efficiency by 2-4 percentage points in production hardware.
Recommended
Server / Telecom SMPS Digital Loop
In 48V-input intermediate bus converters and LLC resonant converters for data-centre PSU applications, the DSPIC33CH128MP205-I/PT drives four high-resolution PWM channels that deliver the dead-band accuracy required for primary-side synchronous rectification. The slave core executes the voltage-mode control loop at full 200 MHz clock, achieving loop bandwidths above 50 kHz that are unreachable on STM32 or LPC-class Cortex-M alternatives. The master core manages PMBus telemetry, fault logging, and the redundant housekeeping tasks. Functional Safety features (lockstep core monitor, ECC on SRAM/Flash, dual-window watchdog) support N+1 redundant PSU designs where IEC 62368-1 compliance is mandatory.
Recommended
BLDC / PMSM Motor Drives (Drones, e-Bikes, Robotics)
Sensorless Field-Oriented Control (FOC) of brushless DC and permanent-magnet synchronous motors benefits from the DSPIC33CH128MP205-I/PT's dual-core partitioning: the slave core runs the 20 kHz current control loop using the 250 ps PWM and the 3.5 Msps ADC's simultaneous sampling of phase currents, while the master executes the slower position/speed estimator and UART/CAN telemetry stack. The hardware Peripheral Trigger Generator (PTG) synchronises ADC samples to PWM edges, eliminating software timing jitter that limits the achievable torque bandwidth. Drone ESC and e-bike controller reference designs from Microchip use this exact partitioning with closed-loop current bandwidths exceeding 5 kHz at 48 V bus.
Recommended
Automotive Safety Sensors (ASIL-B)
Automotive sensors requiring ASIL-B functional safety under ISO 26262 (steering angle sensors, throttle position, brake-by-wire sensors) deploy the DSPIC33CH128MP205-I/PT's FuSa features: lockstep master-slave cores, ECC-protected SRAM/Flash, dual window watchdogs, and hardware BIST. The CAN FD interface supports Automotive Bus architectures where bandwidths above 2 Mbps are needed (CAN FD frames over classical CAN). AEC-Q100 qualified die revisions are marketed as -E/PT or with explicit automotive suffixes; designers must verify the exact ordering code with Microchip for ASIL-B target approval.
Recommended
Digital LED Lighting Drivers
High-density horticultural and architectural LED drivers use the DSPIC33CH128MP205-I/PT's four high-resolution PWM channels to drive multiple parallel boost/flyback stages with 0.01% dimming accuracy at PWM frequencies above 1 MHz, eliminating audible flicker and visible strobing. The slave core services up to four independent LED strings with per-string constant-current regulation while the master core communicates via DALI-2 or DMX512 and runs the colour-mixing algorithm. Compared to simple GPIO-PWM approaches, this architecture achieves ENERGY STAR and DLC Premium dimming compliance without external dimming controllers.
Recommended
Industrial AC-DC Front-End PFC
Power Factor Correction (PFC) stages in industrial AC-DC converters (3 kW to 22 kW) operate the slave core in average-current-mode control loops that require cycle-by-cycle ADC sampling and PWM updates at the 100 kHz switching frequency. The DSPIC33CH128MP205-I/PT's Peripheral Trigger Generator synchronises ADC samples to the PWM zero-cross event, eliminating PWM-edge jitter. The master core handles I2C/PMBus communications, AC mains zero-cross detection, and soft-start sequencing. Convection-cooled industrial designs benefit from the 200 MHz clock headroom that lets the slave core close the loop in well under 1 microsecond on every switching cycle.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33CH128MP205-I/PT β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33CH128MP205-I/M4 | DSPIC33CH128MP205-E/PT | DSPIC33CK128MP205-I/PT |
|---|---|---|---|---|
| Package | TQFP-48 (7x7) | TQFP-48 (7x7) - same | TQFP-48 (7x7) - same | TQFP-48 (7x7) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core Architecture | Dual-core 16-bit DSC | Dual-core 16-bit DSC | Dual-core 16-bit DSC | Single-core 16-bit DSC |
| Max Clock Frequency | 200 MHz per core | 200 MHz per core | 200 MHz per core | 100 MHz single core |
| Flash Memory | 152 KB total (128 KB + 24 KB shared) | 152 KB total | 152 KB total | 128 KB |
| SRAM | 16 KB | 16 KB | 16 KB | 16 KB |
| Temperature Grade | -40 C to +85 C (industrial) | -40 C to +85 C | -40 C to +125 C (extended) | -40 C to +85 C |
| Functional Safety (FuSa) | Yes (lockstep, ECC, BIST) | Yes | Yes | No (lockstep not present) |
Key Differentiators
- Dual-core 16-bit DSC - first of its kind in the dsPIC33 family (vs DSPIC33CK128MP205-I/PT)
- Functional Safety (FuSa) features: lockstep, ECC, hardware BIST (vs DSPIC33EP128GS705-I/PT)
- Higher dual-core clock (180 MHz per core in dual-mode) (vs DSPIC33CK128MP205-I/PT)
- Same TQFP-48 package across CH and CK families (vs DSPIC33CH128MP205-E/PT)
Design Notes
Estimated: at 200 MHz dual-core operation, the DSPIC33CH128MP205-I/PT core logic power consumption is approximately 220 mW at 3.3 V (PWM, ADC, CAN FD active, both cores running). Decouple each VDD/VSS pair with 100 nF X7R ceramic placed within 5 mm of the pin. Add a bulk 10 uF tantalum near the AVDD/AVSS pair and route AVSS directly to the ground plane via a single via. Failing to decouple the AVDD line separately from VDD adds ADC reference noise that couples to current-sense sampling. AVDD must never be supplied from a switching regulator output without LC filtering; use a separate LDO or filter ferrite to achieve <1 mV ripple on AVDD.
Estimated: simultaneous dual-core 200 MHz operation with all peripherals active (PWM, ADC, CAN FD, DMA) dissipates approximately 400 mW. The TQFP-48 (7x7 mm) with exposed thermal pad has theta_JA of approximately 50 C/W on a 2-layer 1 oz PCB, so dual-core operation above 85 C ambient requires a 4-layer PCB with dedicated ground plane and copper pouring over the thermal pad. Place thermal vias in a 4x4 array under the exposed pad; failure to stitch the pad to internal ground layers can raise junction temperature 15-25 C above design target at full dual-core load.
A common pitfall is leaving the slave core uninitialised while configuring shared RAM regions, which causes inter-core variable corruption. Always initialise the slave core's stack pointer and PRAM region from the master during boot via the slave's debug entry point. Second common pitfall: sharing a single DMA channel between cores without explicit ownership tracking causes priority inversion. Assign DMA channels statically (master owns channels 0-3, slave owns 4-7) and document ownership in firmware headers. Third common pitfall: configuring the ADC's Peripheral Trigger Generator (PTG) without aligning the trigger source to the high-resolution PWM reload event, which adds sample-to-PWM jitter that limits control loop bandwidth.
Use a 4-layer PCB stack-up with the second layer as a continuous ground plane routed under the TQFP-48 package. Keep switching PWM output traces (PWMxH/L) routed as short, impedance-controlled microstrip on the top layer. Place the crystal load capacitors within 5 mm of OSCI/OSCO pins and guard the trace with a ground ring to suppress EMI. The CAN FD bus requires a 120 ohm termination at each end of the bus; placing termination inside the DSPIC's package is impossible, so design the PCB with provision for split or single 120 ohm termination.
Compliance Information
Industrial grade (-I/PT) is not AEC-Q100 qualified; Microchip offers AEC-Q100 qualified variants in the -E/PT (extended) and automotive-specific ordering codes. RoHS and lead-free compliance per Microchip product page; halogen-free per industry-standard marking.
