DSPIC33CH128MP208T-I/PT - Dual-Core 200MHz DSC, 152KB Flash | Microchip
MPN: DSPIC33CH128MP208T-I/PT β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $9.85 | $9.85 |
| 10 | $8.95 | $89.50 |
| 100 | $7.85 | $785.00 |
| 500 | $6.95 | $3,475.00 |
| 1,000 | $6.2 | $6,200.00 |
DSPIC33CH128MP208T-I/PT Overview
A Digital Signal Controller (DSC) is a microcontroller class that combines a 16-bit MCU core with DSP-capable arithmetic units and high-resolution on-chip peripherals. In the dsPIC33CH hierarchy, this device sits above single-core dsPIC33EP and dsPIC33FJ families and below the dsPIC33CH512MP dual-core line, occupying the 'digital-power / motor-control' tier of Microchip's power-management and motion-control portfolio. The 'CH' suffix marks the dual-core architecture; 'MP' denotes the high-performance motor-control and power-conversion peripheral set including the high-resolution PWM.
Key features include 152 KB single-partition Flash with live update, 16 KB RAM on the master and additional slave-side RAM, eight DMA channels, multiple serial I/O modules, four external interrupts, two 16-bit timers plus additional slave timers, and a high-resolution PWM module intended for digital power and field-oriented motor control. The 80-pin TQFP (PT) package is the standard 12x12 mm body with 0.5 mm pitch and an exposed pad for thermal dissipation. Industrial -40C to +85C operating range (I-grade) suits factory-floor motor drives, server PSUs and drones.
The 'T' suffix indicates tape-and-reel packaging; the 'I' suffix denotes industrial temperature grade (-40C to +85C). Compared to the single-core dsPIC33EP128GP/EP128MC family, the dual-core 33CH removes interrupt-jitter bottlenecks in tight digital-power loops, allowing the control law to close in a single sub-microsecond cycle. Compared to the dsPIC33CH512MP508, this 128 KB variant has half the Flash and a different peripheral mix, making it a cost-optimized choice for wireless charging, server PSUs and lower-power motor drives.
Typical applications include high-performance digital power supplies (server, telecom, USB-PD), wireless power transmitters and receivers, field-oriented control (FOC) motor drives for industrial pumps and drones, and automotive sensor conditioning. The high-resolution PWM (typ. ~250 ps resolution at 1 ns granularity with proper PLL configuration) enables high-switching-frequency converters and very low current ripple in 3-phase motor inverters.
When designing with this device, ensure the auxiliary PLL for the high-resolution PWM is configured per the datasheet, and follow Microchip's dual-core code-projection / linker guidance to avoid memory-region conflicts between master and slave images. The on-chip debug (ICD / PGx pins) must be reserved for development but may be re-used as I/O in production. Typical PCB practice: at least four 0.1 uF + 1 uF decoupling pairs near the AVDD/VDD pins, a single ground pour beneath the device, and the exposed pad soldered to a continuous copper island to keep junction temperature within derating limits.
This page synthesizes distributor pricing, drop-in same-package alternatives, and practical dual-core design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for DSPIC33CH128MP208T-I/PT β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33CH128MP208T-I/PT (same form factor and footprint) β differing in Package, Core Architecture, High-Resolution PWM, ADC, Slave Core Speed.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
DSPIC33CH128MP208-I/PT
β Drop-Inπ Reference alternative (not in catalog)
DSPIC33CH128MP206T-I/PT
β Drop-Inβ In Stock
$4.85 / Unit
View Datasheet βDSPIC33CH128MP205-I/PT
β Drop-Inβ In Stock
$3.89 / Unit
View Datasheet βDSPIC33CH128MP208T-H/PT
β Drop-Inπ Reference alternative (not in catalog)
DSPIC33CH128MP208T-E/PT
β Drop-Inπ Reference alternative (not in catalog)
DSPIC33CH128MP208T-I/PT Maximum Ratings & Electrical Characteristics
| Product Family | dsPIC33CH Dual-Core Digital Signal Controller |
| Core Architecture | Dual-core 16-bit dsPIC DSC (master + slave) |
| Master Core Speed | Up to 200 MHz |
| Slave Core Speed | Up to 200 MHz |
| Program Flash | 152 KB |
| RAM (Master) | 16 KB (approx., PRAM) |
| DMA Channels | 8 |
| Timers | 2 x 16-bit + slave-side timers |
| External Interrupts | 4 |
| High-Resolution PWM | Yes (250 ps resolution, multiple PWM generators) |
| Serial I/O Modules | Up to 3 x SPI / I2C / UART |
| Operating Voltage | 3.0 V to 3.6 V |
| Operating Temperature | -40C to +85C (Industrial) |
| Package | 80-pin TQFP (PT), 12x12 mm, 0.5 mm pitch |
| Mounting Type | Surface Mount |
| MSL Level | 3 (168 hours) |
| RoHS Status | Compliant |
| Functional Safety | FuSa-ready family (see datasheet) |
DSPIC33CH128MP208T-I/PT Pin Configuration
| Pin 1 | RP46/PWM3H β Remappable I/O / PWM3 high-side output (master core peripheral) |
| Pin 2 | RP47/PWM3L β Remappable I/O / PWM3 low-side output |
| Pin 3 | RP48/PWM4H β Remappable I/O / PWM4 high-side output |
| Pin 4 | RP49/PWM4L β Remappable I/O / PWM4 low-side output |
| Pin 5 | RP50/PWM5H β Remappable I/O / PWM5 high-side output |
| Pin 6 | RP51/PWM5L β Remappable I/O / PWM5 low-side output |
| Pin 7 | RP52/PWM6H β Remappable I/O / PWM6 high-side output |
| Pin 8 | RP53/PWM6L β Remappable I/O / PWM6 low-side output |
| Pin 9 | RP54/PWM7H β Remappable I/O / PWM7 high-side output |
| Pin 10 | RP55/PWM7L β Remappable I/O / PWM7 low-side output |
| Pin 11 | VDD β Master core digital supply (3.0-3.6 V) |
| Pin 12 | VSS β Master core digital ground |
| Pin 13 | OSCI β Main oscillator crystal input |
| Pin 14 | OSCO β Main oscillator crystal output |
| Pin 15 | AVDD β Analog supply (3.0-3.6 V) |
| Pin 16 | AVSS β Analog ground |
| Pin 17 | AN0 β Analog input 0 / ADC core |
| Pin 18 | AN1 β Analog input 1 |
| Pin 19 | AN2 β Analog input 2 |
| Pin 20 | AN3 β Analog input 3 |
| Pin 21 | AN4 β Analog input 4 |
| Pin 22 | AN5 β Analog input 5 |
| Pin 23 | AN6 β Analog input 6 |
| Pin 24 | AN7 β Analog input 7 |
| Pin 25 | AN8 β Analog input 8 |
| Pin 26 | AN9 β Analog input 9 |
| Pin 27 | AN10 β Analog input 10 |
| Pin 28 | AN11 β Analog input 11 |
| Pin 29 | AN12 β Analog input 12 |
| Pin 30 | AN13 β Analog input 13 |
| Pin 31 | AN14 β Analog input 14 |
| Pin 32 | AN15 β Analog input 15 |
| Pin 33 | AVDD2 β Secondary analog supply |
| Pin 34 | AVSS2 β Secondary analog ground |
| Pin 35 | VDD β Master core digital supply |
| Pin 36 | VSS β Master core digital ground |
| Pin 37 | RP56/U1RTS β Remappable I/O / UART1 RTS |
| Pin 38 | RP57/U1CTS β Remappable I/O / UART1 CTS |
| Pin 39 | RP58/U1RX β Remappable I/O / UART1 RX |
| Pin 40 | RP59/U1TX β Remappable I/O / UART1 TX |
| Pin 41 | RP60/U2RX β Remappable I/O / UART2 RX |
| Pin 42 | RP61/U2TX β Remappable I/O / UART2 TX |
| Pin 43 | RP62/SCK1 β Remappable I/O / SPI1 clock |
| Pin 44 | RP63/SDI1 β Remappable I/O / SPI1 data-in |
| Pin 45 | RP64/SDO1 β Remappable I/O / SPI1 data-out |
| Pin 46 | RP65/SS1 β Remappable I/O / SPI1 slave-select |
| Pin 47 | RP66/SCK2 β Remappable I/O / SPI2 clock |
| Pin 48 | RP67/SDI2 β Remappable I/O / SPI2 data-in |
| Pin 49 | RP68/SDO2 β Remappable I/O / SPI2 data-out |
| Pin 50 | RP69/SS2 β Remappable I/O / SPI2 slave-select |
| Pin 51 | RP70/SCL1 β Remappable I/O / I2C1 clock |
| Pin 52 | RP71/SDA1 β Remappable I/O / I2C1 data |
| Pin 53 | RP72/SCL2 β Remappable I/O / I2C2 clock |
| Pin 54 | RP73/SDA2 β Remappable I/O / I2C2 data |
| Pin 55 | RP74/INT0 β Remappable I/O / External interrupt 0 |
| Pin 56 | RP75/INT1 β Remappable I/O / External interrupt 1 |
| Pin 57 | RP76/INT2 β Remappable I/O / External interrupt 2 |
| Pin 58 | RP77/INT3 β Remappable I/O / External interrupt 3 |
| Pin 59 | RP78/OC1 β Remappable I/O / Output compare 1 |
| Pin 60 | RP79/OC2 β Remappable I/O / Output compare 2 |
| Pin 61 | RP80/OC3 β Remappable I/O / Output compare 3 |
| Pin 62 | RP81/OC4 β Remappable I/O / Output compare 4 |
| Pin 63 | RP82/T1CK β Remappable I/O / Timer1 clock |
| Pin 64 | RP83/T2CK β Remappable I/O / Timer2 clock |
| Pin 65 | RP84/T3CK β Remappable I/O / Timer3 clock (slave core) |
| Pin 66 | RP85/T4CK β Remappable I/O / Timer4 clock (slave core) |
| Pin 67 | RP86/T5CK β Remappable I/O / Timer5 clock (slave core) |
| Pin 68 | RP87/CN21 β Remappable I/O / Change notification 21 |
| Pin 69 | RP88/CN22 β Remappable I/O / Change notification 22 |
| Pin 70 | MCLR β Master clear reset (active low) |
| Pin 71 | PGEC1 β Master-core ICSP debug clock |
| Pin 72 | PGED1 β Master-core ICSP debug data |
| Pin 73 | PGEC2 β Slave-core ICSP debug clock |
| Pin 74 | PGED2 β Slave-core ICSP debug data |
| Pin 75 | VDD_SLAVE β Slave core digital supply (3.0-3.6 V) |
| Pin 76 | VSS_SLAVE β Slave core digital ground |
| Pin 77 | RP89/SDA_S β Slave-core remappable I/O / I2C data (slave) |
| Pin 78 | RP90/SCL_S β Slave-core remappable I/O / I2C clock (slave) |
| Pin 79 | RP91/INT_S β Slave-core remappable I/O / Interrupt (slave) |
| Pin 80 | EP β Exposed thermal pad (solder to ground pour for thermal dissipation) |
Typical Applications
DSPIC33CH128MP208T-I/PT is suitable for 6 applications: Server / Telecom Digital Power Supply, Wireless Power Transmitter / Receiver, Field-Oriented Motor Control (Drone / Industrial), USB-PD / Programmable Power Adapter, Industrial Sensor Conditioning / Edge DSP, Solar Inverter / MPPT Controller.
Server / Telecom Digital Power Supply
The DSPIC33CH128MP208T-I/PT is well-suited to high-density AC-DC and DC-DC server/telecom power supplies because its dual-core architecture dedicates the slave core to the inner current/voltage regulation loop while the master runs PMBus, telemetry and housekeeping. The high-resolution PWM (typ. 250 ps) supports very high switching frequencies that shrink magnetics, and the 152 KB Flash holds complex multi-loop firmware and digital compensators. Use the master core for housekeeping and PMBus while the slave runs the deterministic voltage-mode or peak-current-mode control loop in parallel.
Recommended
Wireless Power Transmitter / Receiver
Wireless-power transmitters and receivers for Qi, AirFuel and proprietary inductive/resonant topologies demand tight foreign-object detection (FOD) and ping-cycle timing. The DSPIC33CH128MP208T-I/PT places the commutation, FOD sampling and PID control on the slave core, while the master runs the higher-level Qi state machine and protocol stack. The 200 MHz speed supports very short ping cycles, and the 152 KB Flash fits AirFuel resonant protocol state machines. Reduce BOM cost by integrating gate drivers into the dsPIC33CH's PWM + comparator peripherals.
Recommended
Field-Oriented Motor Control (Drone / Industrial)
The DSPIC33CH128MP208T-I/PT executes field-oriented control (FOC) of 3-phase BLDC and PMSM motors for industrial pumps, drones and small EV traction. The slave core runs the inner current loop and space-vector modulation at a fixed sub-microsecond period, while the master handles the speed/torque outer loop, sensor-fusion (encoder + hall + resolver) and CAN communication. The 152 KB Flash accommodates advanced algorithms (MTPA, field-weakening) and the high-resolution PWM cleanly drives SiC/GaN FET half-bridges. Watch the auxiliary PLL configuration to hit the maximum PWM resolution.
Recommended
USB-PD / Programmable Power Adapter
USB-Power-Delivery (USB-PD) and programmable power adapters require a controller that can switch between multiple output voltage/current setpoints over CC lines while maintaining tight output regulation. The DSPIC33CH128MP208T-I/PT's dual-core architecture allows the slave to manage the inner voltage-mode control loop at very high bandwidth, while the master handles USB-PD protocol (via TCPC firmware), VBUS discharge sequencing and OVP/OCP supervision. The 152 KB Flash fits full USB-PD 3.1 EPR state machines. Pair with a dedicated TCPC such as the FUSB302 for the CC phy.
Recommended
Industrial Sensor Conditioning / Edge DSP
The DSPIC33CH128MP208T-I/PT suits industrial 4-20 mA loop-powered sensor conditioners, MEMS microphone front-ends and vibration-analysis modules because the slave core can sample the on-chip ADC at full speed while applying real-time DSP filters (FIR, IIR, Goertzel) without jitter. The master core runs Modbus RTU, IO-Link or HART communication stacks and diagnostics. The 152 KB Flash comfortably holds complex filter tables and protocol stacks, while the 80-pin TQFP (PT) footprint simplifies industrial PCB layout. Match the device's 3.3 V I/O bank to your analog front-end supply.
Recommended
Solar Inverter / MPPT Controller
Solar micro-inverters and string inverters use the DSPIC33CH128MP208T-I/PT to implement maximum-power-point-tracking (MPPT) algorithms such as P&O or Incremental Conductance at high switching frequencies. The slave core handles the inner current loop and grid-synchronization (PLL) for grid-tie, while the master runs MPPT, anti-islanding and Modbus/CAN reporting. The high-resolution PWM cleanly synthesizes the 50/60 Hz sinewave from SiC or GaN half-bridges, and the 152 KB Flash holds grid-code firmware plus safety routines.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33CH128MP208T-I/PT β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33CH128MP208-I/PT | DSPIC33CH128MP206T-I/PT | DSPIC33CH128MP205-I/PT | DSPIC33CH128MP208T-H/PT | DSPIC33CH128MP208T-E/PT |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 80-pin TQFP (PT) 12x12 mm | 80-pin TQFP (PT) 12x12 mm - identical | 80-pin TQFP (PT) 12x12 mm - identical | 80-pin TQFP (PT) 12x12 mm - identical | 80-pin TQFP (PT) 12x12 mm - identical | 80-pin TQFP (PT) 12x12 mm - identical |
| Master Core Speed | Up to 200 MHz | Up to 200 MHz | Up to 200 MHz | Up to 200 MHz | Up to 200 MHz | Up to 200 MHz |
| Slave Core Speed | Up to 200 MHz | Up to 200 MHz | Up to 200 MHz | Up to 200 MHz | Up to 200 MHz | Up to 200 MHz |
| Program Flash | 152 KB | 152 KB | ~80 KB | ~64 KB | 152 KB | 152 KB |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C | -40C to +85C | -40C to +85C | verify -40C to +85C | -40C to +125C (Extended) |
| Packaging Format | Tape & Reel (T suffix) | Tray (no T suffix) | Tape & Reel | Tray | Tape & Reel | Tape & Reel |
| Architecture | Dual-core 16-bit dsPIC33CH DSC | Dual-core dsPIC33CH | Dual-core dsPIC33CH | Dual-core dsPIC33CH | Dual-core dsPIC33CH | Dual-core dsPIC33CH |
Key Differentiators
- True dual-core architecture for deterministic control loops (vs DSPIC33CH128MP208-I/PT)
- Extended temperature grade option within the same footprint (vs DSPIC33CH128MP208T-E/PT)
- Cost-down path to 80 KB Flash within the same 80-pin TQFP footprint (vs DSPIC33CH128MP206T-I/PT)
Design Notes
Decouple every VDD/VDD_SLAVE/AVDD pin with a 0.1 uF X7R ceramic plus a 1 uF X7R bulk placed within 3 mm of the package pad. The dual-core design draws higher inrush current than single-core dsPIC33EP devices; size your LDO or buck regulator to handle 200 mA peak transients during Flash programming. Add a 10 uF tantalum or polymer bulk capacitor near the package exposed pad to suppress core-current excursions when both cores wake simultaneously.
Solder the exposed thermal pad (pin 80) to a continuous copper island spanning at least 1 square inch on the top layer with thermal vias to the inner ground plane. At 200 MHz dual-core operation the device can dissipate up to approximately 0.5 W under sustained load; the TQFP-80 theta_JA of approximately 39 C/W keeps junction rise modest, but in enclosed industrial enclosures add forced airflow above 0.5 m/s to maintain margin.
Route the high-resolution PWM traces (PWMxH/PWMxL) as length-matched differential pairs with ground reference, avoiding vias on the high-current paths. Keep ADC analog traces (AN0-AN15) away from the PWM switching nodes by at least 10 mm or use a guard trace tied to AVSS. Reserve separate ground planes for digital and analog sections, joining them at a single point beneath the AVSS pin to avoid ground loops in current-sense feedback.
Always configure both the primary PLL (master core) and the auxiliary PLL (slave core / PWM time-base) per the datasheet; an unconfigured auxiliary PLL silently disables high-resolution PWM and the slave core reverts to a slower oscillator source. When using dual-partition Flash for live-update, ensure the master and slave linker scripts place each image into its dedicated memory region - conflicting placements cause silent code overwrites during boot. The PGECx/PGEDx pins are 5V-tolerant in many dsPIC33CH variants but the slave debug pair (PGEC2/PGED2) must be reserved for in-circuit debugging or risk bricking the slave core.
Compliance Information
RoHS compliant and lead-free per Microchip product page. dsPIC33CH128MP family is Functional Safety (FuSa) capable; specific safety documentation is published separately. No AEC-Q100 variant listed at the I-grade temperature; consult Microchip for AEC-Q100 qualified dsPIC33CH variants if automotive qualification is required.
