DSPIC33CK64MP105-I/PT - 100MHz 16-bit DSC 64KB Flash | Microchip
MPN: DSPIC33CK64MP105-I/PT ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3.2 | $3.20 |
| 10 | $2.9 | $29.00 |
| 100 | $2.6 | $260.00 |
| 500 | $2.45 | $1,225.00 |
| 1,000 | $2.35 | $2,350.00 |
DSPIC33CK64MP105-I/PT Overview
A digital signal controller combines the compute capability of a microcontroller with the mathematical throughput of a DSP. Within the power-management hierarchy, a DSC sits above a generic MCU: it executes a 16-bit modified Harvard architecture with an enhanced instruction set and dedicated DSP support, enabling closed-loop control loops (current, voltage, speed) at very high sampling rates in digital power and motor drive systems.
Key features of the dsPIC33CK64MP10X family include a single dsPIC DSC core running at 100 MIPS, integrated DSP multiply-accumulate hardware, 12-bit ADCs with high sample rates, multiple internal op amps for current-sense conditioning, analog comparators, and advanced PWM modules with fine edge placement - all essential for fast, deterministic control of switching power stages and motor phases.
Technically, the CPU uses a 16-bit modified Harvard architecture with an enhanced instruction set including significant DSP support, according to the Microchip dsPIC33CK64MP105 family data sheet (DS70005363E). The family is documented as enabling digital power, motor control, advanced sensing, and companion/co-processing designs.
Typical applications include digital power supplies (LLC, totem-pole PFC), BLDC/PMSM motor drives, high-performance general-purpose embedded control, and advanced sensing front ends where the on-chip op amps and high-speed ADC replace external analog signal-conditioning components.
Design consideration: all VDD/VSS pins must be connected and decoupled, and ICSP programming requires using PGECx/PGEDx pin pairs as matched pairs - connect ICSPCLK/ICSPDAT to the same numbered pair.
This page synthesizes distributor pricing, drop-in alternatives within the same 48-pin TQFP footprint, pinout guidance, and practical design notes not found in a single datasheet page.
Drop-in alternatives for DSPIC33CK64MP105-I/PT — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33CK64MP105-I/PT (same form factor and footprint) — differing in Core, Package, Operating Temperature, PWM, Architecture.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33CK64MC105T-I/M4
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View Datasheet →DSPIC33CK32MP506-E/MR
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$3.55 / Unit
View Datasheet →DSPIC33CK256MP205-I/PT
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$3.55 / Unit
View Datasheet →DSPIC33CH64MP506T-I/PT
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$2.74 / Unit
View Datasheet →DSPIC33CK512MP606T-I/PT
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View Datasheet →DSPIC33CK128MP205-E/PT
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$3.61 / Unit
View Datasheet →DSPIC33CK64MP105-I/PT Maximum Ratings & Electrical Characteristics
| Core | 16-bit dsPIC DSC, single core |
| CPU Speed | 100 MHz (100 MIPS) |
| Flash Memory | 64 KB |
| RAM | 8 KB |
| Architecture | 16-bit modified Harvard with DSP support |
| ADC Resolution | 12-bit |
| On-Chip Op Amps | Yes |
| Comparators | Yes |
| PWM | High-resolution PWM |
| CAN FD | Yes (5XX subfamily) |
| Operating Temperature | -40C to +85C |
| Package | 48-pin TQFP (7x7 mm) |
| Mounting Type | Surface Mount |
| Programming Interface | ICSP (PGECx/PGEDx pairs) |
| RoHS Status | Compliant |
| Typical Applications | Digital power, motor control, advanced sensing |
DSPIC33CK64MP105-I/PT 48-pin tqfp (7x7 mm) Pin Configuration Guide
Pin configuration for DSPIC33CK64MP105-I/PT (48-pin tqfp (7x7 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for DSPIC33CK64MP105-I/PT.
Refer to the datasheet for full pin configuration.
Typical Applications
DSPIC33CK64MP105-I/PT is suitable for 6 applications: Digital Power Supplies (LLC, PFC), BLDC/PMSM Motor Control, Advanced Sensing Front Ends, High-Performance General-Purpose Embedded Control, Companion / Co-Processing Designs, Automated Industrial and Robotics Nodes.
Digital Power Supplies (LLC, PFC)
The DSPIC33CK64MP105-I/PT fits digital power conversion because its 100 MIPS core closes current and voltage loops fast enough for 100 kHz+ LLC and totem-pole PFC stages, while the 12-bit high-speed ADC samples inductor current and output voltage with the timing precision the high-resolution PWM requires. The on-chip op amps condition shunt or inductor DCR current-sense signals internally, removing external amplifier ICs from the feedback path, and analog comparators support cycle-by-cycle overcurrent protection without CPU intervention. Place the DSC between the sensing network and the gate drivers with the PWM module driving half-bridge gates; the trade-off versus a fixed-function controller is firmware complexity in exchange for full configurability of modulation schemes and protection thresholds.
Recommended
BLDC/PMSM Motor Control
Motor drives benefit directly from the DSPIC33CK64MP105-I/PT's integrated analog front end: the on-chip op amps amplify low-level current-shunt signals from up to three motor phases, the 12-bit ADCs trigger synchronously with PWM centers to minimize switching-noise corruption, and the high-resolution PWM generates complementary outputs with dead-time control for FOC or sensorless trapezoidal commutation. The 100 MIPS core executes field-oriented control loops including Clarke/Park transforms and PI current regulators within one PWM period. Microchip's MCLV-2 (DM330021-2) and MCHV-2/MCHV-3 boards with the MA330050-1 PIM provide ready-made motor control hardware using this exact 48-pin device, letting engineers validate FOC firmware before committing to a custom PCB.
Recommended
Advanced Sensing Front Ends
The DSPIC33CK64MP105-I/PT suits advanced sensing applications where analog conditioning and DSP post-processing must coexist in a single chip. The integrated op amps can be configured as programmable-gain amplifiers for sensor signals, the 12-bit ADCs digitize multiple channels with flexible scan sequencing, and the 100 MHz DSP engine applies digital filters (IIR/FIR with MAC acceleration) to extracted measurements in real time. This integration reduces BOM count versus discrete amplifier-plus-MCU solutions and shortens the analog signal path, improving noise immunity. Typical uses include precision current monitoring, vibration and acoustic analysis, and industrial condition monitoring where the -40C to +85C industrial temperature grade and DSP throughput handle both the acquisition and the algorithms on one 48-pin TQFP device.
Recommended
High-Performance General-Purpose Embedded Control
As a general-purpose embedded controller, the DSPIC33CK64MP105-I/PT offers 100 MIPS of 16-bit processing, 64 KB flash, and 8 KB RAM - enough headroom for communication stacks, state machines, and moderate control algorithms while retaining the deterministic execution of the dsPIC33C core. Peripherals inherited from the digital-power lineage (fast comparators, high-resolution PWM, high-speed ADC) also serve non-power tasks such as LED dimming, ultrasonic drivers, and closed-loop positioning. CAN FD support on the 5XX subfamily enables industrial networked nodes. Developers work in MPLAB X with the XC16 compiler and debug via ICSP using any PGECx/PGEDx pair (kept as matched pairs). This part is a strong choice when a design outgrows an 8-bit PIC16 family device but does not need a 32-bit ARM-class MCU.
Recommended
Companion / Co-Processing Designs
Microchip positions the dsPIC33CK64MP10X family for companion and co-processing roles alongside host processors: a single-core 100 MHz DSC can offload time-critical tasks - power sequencing, battery charging control, motor sub-system control, or DSP filtering - from a main application CPU over UART, SPI, I2C, or CAN FD. The architecture is intentionally similar to the dual-core dsPIC33CH, per community architecture notes, which eases migration if the design later consolidates into a dual-core dsPIC33CH part such as the DSPIC33CH64MP506T-I/PT. In this role the 8 KB RAM and 64 KB flash bound the offloaded firmware scope, so partition firmware with real-time duties only, reserving UI and protocol stacks for the host. This yields deterministic latency on the offloaded loop and simplifies host software.
Recommended
Automated Industrial and Robotics Nodes
Industrial automation nodes use the DSPIC33CK64MP105-I/PT to combine real-time actuator control with network connectivity: CAN FD (5XX subfamily) links the node to factory buses while the 100 MIPS core runs servo or stepper commutation locally. The high-resolution PWM drives gate drivers or stepper drivers, on-chip comparators provide hardware-level overcurrent trips that respond faster than any interrupt, and the industrial -40C to +85C grade suits control cabinets and machine-mounted electronics. The Motor Control Stepper Motor (MCSM) development path from Microchip, which supports the MA330050-1 PIM, demonstrates stepper motion control on this exact silicon. Designers should route PWM traces away from analog sense lines and decouple all VDD/VSS pairs to maintain ADC accuracy in electrically noisy cabinets.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33CK64MP105-I/PT — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33CK64MC105T-I/M4 | DSPIC33CK256MP205-I/PT | DSPIC33CK128MP205-E/PT | DSPIC33CK32MP506-E/MR | DSPIC33CH64MP506T-I/PT |
|---|---|---|---|---|---|---|
| Package | TQFP-48 (7x7 mm) | TQFP-48 (7x7 mm) - same | TQFP-48 (7x7 mm) - same | TQFP-48 (7x7 mm) - same | TQFP-64 | TQFP-64 |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| CPU Speed | 100 MHz (100 MIPS) | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz (slave core, plus master CPU) |
| Flash Memory | 64 KB | 64 KB | 256 KB | 128 KB | 32 KB | 64 KB |
| Core Count | 1 (single core) | 1 | 1 | 1 | 1 | 2 (master + slave) |
| Operating Temperature | -40C to +85C (industrial, -I grade) | -40C to +85C | -40C to +85C | Extended (-E grade) | Extended (-E grade) | -40C to +85C |
| On-Chip Op Amps / ADC Emphasis | MP variant: op amps, 12-bit high-speed ADC, comparators | MC variant (reduced analog emphasis) | MP variant: op amps, 12-bit ADC | MP variant: op amps, 12-bit ADC | MP variant: op amps, 12-bit ADC | CH variant: dual-core control emphasis |
Key Differentiators
- Integrated analog front end (op amps + 12-bit high-speed ADC + comparators) (vs DSPIC33CK64MC105T-I/M4)
- Largest flash in the same TQFP-48 footprint (vs DSPIC33CK256MP205-I/PT)
- Single-core simplicity vs dual-core partitioning (vs DSPIC33CH64MP506T-I/PT)
Design Notes
Connect every VDD and VSS pin pair and decouple each with a 100 nF ceramic capacitor placed within 2 mm of the pin, per Microchip family design guidance. The dsPIC33CK64MP105 has multiple VDD/VSS pairs plus separate AVDD/AVSS for the analog domain; star-route AVDD through an RC or ferrite filter from the digital rail to preserve 12-bit ADC accuracy. For ICSP programming, route a 5-pin header to one PGECx/PGEDx pair - use ICSPCLK and ICSPDAT from the same numbered pair (for example PGEC2 with PGED2), never mix pairs.
Two pitfalls recur in dsPIC33CK designs. First, peripheral registers on the CK family are not compatible with older dsPIC30F/33F ranges - code ported from dsPIC33F requires UART, timer, and PWM driver rewrites per community architecture documentation. Second, flash budget: 64 KB flash and 8 KB RAM fill quickly once FOC math, communication stacks, and diagnostics are included; if your firmware exceeds roughly 50 KB, select the 128 KB or 256 KB flash sibling (DSPIC33CK128MP205, DSPIC33CK256MP205) in the same TQFP-48 footprint before layout freeze.
In digital power and motor control layouts, keep the PWM output traces to gate drivers short and away from the current-sense lines feeding the on-chip op amps; synchronous ADC sampling triggered by the PWM module mitigates switching-noise corruption, but physical separation still matters. Place the current-shunt sensing network close to the device so the op amp inputs see short, Kelvin-routed traces. Use a solid ground plane under the TQFP with the thermal path through the package leads; the 7x7 mm TQFP dissipates modest power so no heatsink is needed at typical 3.3 V operation.
Compliance Information
RoHS compliant and lead-free per LCSC product listing (C648131) and DigiKey. REACH and halogen-free status not stated in provided data.
