DSPIC33FJ128GP310-I/PT - 16-bit DSC 40 MIPS 128KB Flash | Microchip
MPN: DSPIC33FJ128GP310-I/PT ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6.62 | $6.62 |
| 10 | $5.95 | $59.50 |
| 100 | $5.3 | $530.00 |
| 500 | $4.85 | $2,425.00 |
| 1,000 | $4.4 | $4,400.00 |
DSPIC33FJ128GP310-I/PT Overview
A digital signal controller blends the control peripherals of a microcontroller (MCU) with the math acceleration of a digital signal processor (DSP) in a single chip. Within the power-management hierarchy of embedded systems, the dsPIC33F family sits between general-purpose PIC24 MCUs and dedicated DSPs, offering seamless code migration options to both PIC24 MCUs and dsPIC30F DSCs, as stated by Microchip.
Key differentiating features include the 16-bit modified Harvard architecture executing up to 40 MIPS at 40 MHz, 128 KB of self-programmable Flash for code storage, a rich analog and digital peripheral set (high-speed ADC, PWM, UART/SPI/I2C serial ports), and an industrial temperature rating of -40C to +85C denoted by the -I suffix.
Technically, the device integrates DSP-class multiply-accumulate instructions, two address generation units and hardware loop support, allowing FIR/IIR filtering and control-loop math to run efficiently without an external DSP. In-Circuit Serial Programming (ICSP) via any PGECx/PGEDx pin pair enables field updates with just two I/O pins plus reset.
Typical applications include motor control (FOC and sensorless BLDC), digital power supplies, industrial automation, and audio or sensor signal conditioning where MCU flexibility and DSP throughput are both required.
Design consideration: all VDD and VSS pins must be connected, and the selected PGEC2/PGED2 pair must be used together for programming, or ICSP will fail, as emphasized in Microchip programming documentation.
This page adds value beyond the datasheet by consolidating distributor pricing, pin-compatible drop-in alternatives, design notes, and an application selection guide not found in the manufacturer's documentation.
Drop-in alternatives for DSPIC33FJ128GP310-I/PT — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33FJ128GP310-I/PT (same form factor and footprint) — differing in Core Architecture, Package, Series, Operating Temperature, Maximum CPU Speed.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33FJ256GP310-I/PT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ64GP310-I/PT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ128GP710-I/PT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ256GP710-I/PT
✅ Drop-In✓ In Stock
$9.9 / Unit
View Datasheet →DSPIC33FJ128GP310A-I/PT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ128GP310-I/PT Maximum Ratings & Electrical Characteristics
| Core Architecture | 16-bit dsPIC33F DSC |
| Maximum CPU Speed | 40 MIPS (40 MHz) |
| Program Memory Size | 128 KB Flash |
| Program Memory Type | Flash (self-programmable) |
| Operating Voltage Range | 3.0 V to 3.6 V |
| Package | TQFP-100 |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +85C (Industrial) |
| Series | dsPIC33FJ128GPx10 |
| Programming Interface | ICSP (2-wire, PGECx/PGEDx pairs) |
| Communication Interfaces | UART, SPI, I2C |
| RoHS Status | Compliant |
| Migration Path | Seamless to PIC24 MCU and dsPIC30F DSC |
DSPIC33FJ128GP310-I/PT tqfp-100 Pin Configuration Guide
Pin configuration for DSPIC33FJ128GP310-I/PT (tqfp-100 package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for DSPIC33FJ128GP310-I/PT.
Refer to the datasheet for full pin configuration.
Typical Applications
DSPIC33FJ128GP310-I/PT is suitable for 6 applications: Sensorless BLDC and FOC Motor Control, Digital Power Supplies and Converters, Industrial Automation and PLC I/O, Audio Signal Processing, Battery-Powered Portable Instruments, Embedded Networking and Gateway Nodes.
Sensorless BLDC and FOC Motor Control
The DSPIC33FJ128GP310-I/PT is well suited to field-oriented control (FOC) and sensorless BLDC motor drives because its 16-bit DSP core executes multiply-accumulate instructions at 40 MIPS, closing current loops fast enough for PWM frequencies in the tens of kHz. The fast ADC samples phase currents synchronized to the PWM center, while hardware loop support reduces ISR overhead in Clarke/Park transforms and PI compensators. In a typical drive, the DSC generates complementary PWM with dead-time for a three-phase inverter and reads the rotor position from a back-EMF observer or resolver. Unlike 8-bit MCUs, the single-cycle MAC keeps control-loop jitter low, and 128 KB Flash holds position tables plus a communication stack. All VDD pins must be connected for reliable ICSP debugging in noisy drive environments.
Recommended
Digital Power Supplies and Converters
In digitally controlled AC-DC and DC-DC converters, the DSPIC33FJ128GP310-I/PT replaces analog compensators with firmware running on its 40 MIPS core. The high-speed ADC samples output voltage and inductor current each switching cycle, and the DSP multiply-accumulate engine implements PID or 3-pole/3-zero compensators with deterministic latency. Its PWM peripherals support complementary outputs, dead-time insertion, and cycle-by-cycle current limiting needed for half-bridge, LLC, and PFC stages. Operating from a 3.0-3.6 V supply, it interfaces cleanly with isolated feedback via digital isolators. The 128 KB Flash supports firmware-updatable power supplies with adaptive tuning - a key advantage over fixed analog control - while the -40C to +85C industrial rating suits telecom rectifiers and server PSUs. Power-stage layout must keep PWM switching nodes away from the analog ADC inputs.
Recommended
Industrial Automation and PLC I/O
Factory automation nodes benefit from the GP310's blend of DSP throughput and MCU peripherals. The 100-pin TQFP provides abundant I/O for driving relays, reading encoders, and interfacing HMI displays, while UART, SPI, and I2C links connect to RS-485 transceivers, RTCs, and EEPROM. The 40 MIPS DSP engine runs FFT-based vibration monitoring and digital filtering directly on the node, reducing host traffic. With a -40C to +85C industrial rating and 3.0-3.6 V operation from a shared 3.3 V rail, the part fits control cabinets without extra thermal design at moderate loads. Firmware updates in the field are performed over ICSP using any matched PGECx/PGEDx pair, and 128 KB Flash accommodates bootloader plus application code. Remember that all VDD and VSS pins must be connected, or programming and brown-out behavior may fail in the cabinet.
Recommended
Audio Signal Processing
The dsPIC33FJ GP310 serves cost-sensitive audio products such as active crossovers, EQ presets, and speech codecs, where its 40 MIPS single-cycle MAC executes biquad filters and mixing at 48 kHz sample rates with margin to spare. The on-chip fast ADC digitizes microphone or line inputs, and codec chips connect via the serial interfaces (SPI/I2C or DCI-style framing on family members that support it). Running at 3.3 V, it pairs with common audio DACs and headphone amplifiers without level shifting. Compared with a dedicated audio DSP, the GP310 integrates control functions - buttons, encoders, display driving - in the same chip, cutting BOM count. The -40C to +85C rating also covers automotive-adjacent and outdoor installed audio. Designers should budget Flash carefully: 128 KB holds substantial coefficient tables and preset storage for multi-band processing chains.
Recommended
Battery-Powered Portable Instruments
Handheld measurement and data-logging instruments use the DSPIC33FJ128GP310-I/PT for its single-supply 3.0-3.6 V operation, which maps directly onto a Li-ion cell via an LDO, and its DSP capability for on-device signal analysis such as RMS computation and FFT-based spectral inspection. The 100-pin TQFP drives segment LCDs, keypads, and USB-bridge ICs through its many I/O pins, while 128 KB Flash retains calibration tables and a bootloader for field upgrades via the two-wire ICSP interface. The -40C to +85C industrial rating supports outdoor and cold-chain instruments. Compared with larger DSPs, quiescent overhead stays low enough for battery operation when peripherals are clock-gated in idle modes. Layout note: keep the analog front-end ground separate from the digital return and connect all VSS pins to minimize measurement noise coupling into ADC readings.
Recommended
Embedded Networking and Gateway Nodes
Protocol-translation gateways built on the GP310 link field buses (RS-485, CAN via external transceivers) to upstream Ethernet or USB bridges. The 40 MIPS core handles checksum computation, packet filtering, and buffering in DSP-style loops, while the UART, SPI, and I2C ports terminate multiple lower-speed channels concurrently. Its 128 KB Flash stores dual firmware images for fail-safe OTA updates, and matched PGEC/PGED programming pairs allow production programming of fully assembled boards. Operating at 3.0-3.6 V with a -40C to +85C range, the controller suits unconditioned industrial enclosures. The 100-pin package leaves headroom for status LEDs, DIP switches, and supervisor logic. For reliability, use the configuration bits to enable brown-out reset and watchdog timer, since gateway nodes must self-recover from bus faults without human intervention, and verify that every VDD/VSS pair is decoupled with 100 nF ceramics.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33FJ128GP310-I/PT — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33FJ256GP310-I/PT | DSPIC33FJ64GP310-I/PT | DSPIC33FJ128GP710-I/PT | DSPIC33FJ256GP710-I/PT |
|---|---|---|---|---|---|
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| CPU Performance | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS |
| Flash Memory | 128 KB | 256 KB | 64 KB | 128 KB | 256 KB |
| Operating Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| Operating Temperature | -40C to +85C (I) | -40C to +85C (I) | -40C to +85C (I) | -40C to +85C (I) | -40C to +85C (I) |
| Core Type | 16-bit dsPIC33F DSC | 16-bit dsPIC33F DSC | 16-bit dsPIC33F DSC | 16-bit dsPIC33F DSC (GP710 pinout) | 16-bit dsPIC33F DSC (GP710 pinout) |
| Pin Compatibility with GP310 | Reference (100-pin TQFP) | Pin-to-pin | Pin-to-pin | Same footprint, verify peripheral pin mapping | Same footprint, verify peripheral pin mapping |
Key Differentiators
- Double the Flash capacity upgrade path (vs DSPIC33FJ64GP310-I/PT)
- Cost-optimized over the 256 KB variant (vs DSPIC33FJ256GP310-I/PT)
- Same die, errata-corrected silicon available (vs DSPIC33FJ128GP310A-I/PT)
Design Notes
Connect every VDD and VSS pin pair on the 100-pin TQFP - Microchip programming documentation explicitly warns that if even one supply pin is left unconnected, ICSP programming may fail. Place a 100 nF X7R ceramic decoupling capacitor within 2 mm of each VDD/VSS pair, plus one bulk 4.7-10 uF capacitor per supply domain. The VDDCORE pin requires its own decoupling network per the family datasheet power section; omitting it causes erratic brown-out behavior at 3.0 V operation near the low end of the 3.0-3.6 V range.
The GP310 offers more than one PGECx/PGEDx pair for ICSP. You may use any pair, but the clock and data must come from the SAME pair (e.g., PGEC2 with PGED2) - mixing pins from different pairs is a common cause of 'target device not found' errors in MPLAB IPE. Reserve the chosen pair on your schematic with a 5-pin programming header (MCLR, VDD, GND, PGECx, PGEDx) and avoid loading these pins with pull-downs or capacitors greater than a few hundred pF during programming.
Keep the high-speed PWM outputs and any switching power stage physically separated from ADC input traces on the 100-pin TQFP. Route analog sense lines on an inner layer with a guard ground, and use an RC anti-alias filter (e.g., 1 kΩ + 1 nF) at each ADC channel when sampling motor currents synchronized to PWM events. At 40 MIPS, interrupt jitter from ESD/EMI events translates directly into control-loop error in FOC drives, so enable the watchdog and brown-out reset configuration bits in all industrial deployments.
Estimated: at 40 MIPS and 3.3 V, typical core current for this class of dsPIC33F device is on the order of tens of milliamps, giving chip dissipation well under 0.5 W - well within the TQFP-100 natural-convection capability without heatsinking. Verify with the family datasheet electrical characteristics for your exact clock configuration; if running continuously near 40 MHz with many active peripherals, a 2 oz. copper ground pour under the package keeps junction temperature comfortably below the 125C absolute maximum in 85C ambient environments.
Compliance Information
RoHS compliance per standard Microchip commercial-grade listing on distributor pages; REACH and halogen-free status not explicitly stated in the provided web data.
