DSPIC33FJ128GP310A-I - 16-bit 40MIPS 128KB Flash DSC | Microchip
MPN: DSPIC33FJ128GP310A-I ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.2 | $7.20 |
| 10 | $6.55 | $65.50 |
| 100 | $5.9 | $590.00 |
| 500 | $5.4 | $2,700.00 |
| 1,000 | $4.95 | $4,950.00 |
DSPIC33FJ128GP310A-I Overview
A Digital Signal Controller combines the computational architecture of a Digital Signal Processor (DSP) with the peripheral integration and control-oriented instruction set of a microcontroller. Within the power management hierarchy of embedded systems, the DSC sits between a general-purpose MCU and a dedicated DSP: it executes single-cycle MAC and DSP-style multiply instructions while retaining deterministic interrupt latency and byte-addressable SRAM typical of PIC MCUs.
Key features of the dsPIC33FJ128GP310A include a 16-bit modified Harvard architecture CPU with DSP instruction extensions, up to 40 MIPS at 3.3V supply, an operating voltage range of 3.0V to 3.6V, and rich analog and digital peripherals on the GP (General Purpose, audio-capable) variant. The A revision integrates errata fixes relative to the original dsPIC33FJ128GP310 silicon and is recommended for all new designs.
The device architecture pairs the CPU with multiple interrupt-prioritized peripherals, dual ADC modules suited for simultaneous multi-channel sampling, UART/SPI/I2C communication ports, and output-compare/input-capture timers. Flash program memory supports self-write for field upgrades, and the industrial temperature rating (-40C to +85C, suffix I) suits harsh deployed environments.
Typical applications include motor control (FOC/field-oriented control of BLDC and PMSM machines), digital power supplies and PFC stages, industrial automation nodes, embedded audio processing, and sensing platforms requiring both fast math and peripheral-rich I/O.
A key design consideration: at 40 MIPS the core current draw concentrates thermal load on the TQFP paddle-adjacent pins - provide solid ground pours and decoupling on all VDD/VSS pairs, and verify worst-case current from the manufacturer datasheet electrical specifications before finalizing the 3.3V rail budget.
This page synthesizes distributor pricing (LCSC/DigiKey/Mouser as of 2026-09-26), drop-in alternatives within the dsPIC33FJ 100-pin family, and practical design notes not consolidated on the manufacturer product page, giving engineers and buyers a single citable reference.
Drop-in alternatives for DSPIC33FJ128GP310A-I — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33FJ128GP310A-I (same form factor and footprint) — differing in Core Architecture, Maximum CPU Speed, Operating Temperature, Package, Series.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33FJ128GP310-I/PT
✅ Drop-In✓ In Stock
$4.4 / Unit
View Datasheet →DSPIC33FJ64GP310A-I/PT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ256GP310A-I/PT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ128GP710A-I/PT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ256GP710A-I/PT
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$15.6 / Unit
View Datasheet →DSPIC33FJ128MC510A-I/PT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ128GP310A-I Maximum Ratings & Electrical Characteristics
| Core Architecture | 16-bit dsPIC33F modified Harvard, DSP-enhanced |
| Maximum CPU Speed | 40 MIPS |
| Flash Program Memory | 128 KB |
| SRAM | 16 KB |
| Supply Voltage Range | 3.0 V to 3.6 V |
| Operating Temperature | -40C to +85C (I suffix, industrial) |
| Package | 100-pin TQFP, 14 x 14 mm (PT suffix) |
| Mounting Type | Surface Mount |
| Series | dsPIC33FJ128GP310A (A-step silicon) |
| Product Type | Digital Signal Controller (DSC), GP (General Purpose / audio-capable) family |
| ADC Resolution | 12-bit |
| Communication Interfaces | UART, SPI, I2C |
| Timers / Capture-Compare | Output Compare and Input Capture channels with timers |
| In-Circuit Programming | Yes (ICSP via programming/debug interface) |
| Automotive Qualification | Not AEC-Q100 qualified (choose -E or AEC variants where offered) |
DSPIC33FJ128GP310A-I 100-pin tqfp, 14 x 14 mm (pt suffix) Pin Configuration Guide
Pin configuration for DSPIC33FJ128GP310A-I (100-pin tqfp, 14 x 14 mm (pt suffix) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for DSPIC33FJ128GP310A-I.
Refer to the datasheet for full pin configuration.
Typical Applications
DSPIC33FJ128GP310A-I is suitable for 6 applications: Field-Oriented Motor Control (BLDC/PMSM), Digital Power Supplies and PFC, Embedded Audio Processing, Industrial Automation Nodes, Sensor Fusion and Data Acquisition, Embedded Control with Field Upgradability.
Field-Oriented Motor Control (BLDC/PMSM)
The DSPIC33FJ128GP310A-I fits motor control because its 40 MIPS DSP-enhanced core executes single-cycle MAC and 40-bit accumulate operations required for field-oriented control loops running at 10-20 kHz PWM frequencies. The 12-bit ADC enables fast current and position feedback sampling synchronized to the PWM cycle, while output-compare channels generate the complementary drive waveforms. In a typical FOC topology, the DSC samples phase currents twice per PWM period, executes Clarke/Park transforms and PI current loops in a few microseconds, and still retains headroom for the outer speed loop and communication. The -40C to +85C industrial rating matches drive environments, and 128 KB Flash accommodates sensorless estimators without external memory.
Recommended
Digital Power Supplies and PFC
Digital power conversion demands deterministic, fast control loops, and the dsPIC33FJ GP310A delivers them with its 40 MIPS core and DSP MAC instructions executing compensator calculations in single-digit microseconds. The 12-bit ADC can be triggered precisely off the PWM timebase, allowing cycle-by-cycle current sensing in buck, boost, or PFC topologies, while output-compare channels produce the switching waveforms with programmable dead-time handling in software. Running the control law entirely in firmware lets engineers implement nonlinear or adaptive compensation impossible with analog controllers. The 3.0V-3.6V core supply simplifies bias architecture, and in-circuit self-write of Flash supports field firmware updates of control parameters in deployed power hardware.
Recommended
Embedded Audio Processing
The GP (General Purpose, audio-capable) designation of the dsPIC33FJ128GP310A makes it appropriate for embedded audio: filtering, audio effects, and codec interfacing. The 40 MIPS core sustains multiple biquad IIR filter stages or moderate FFT workloads per audio block, and the serial peripherals (SPI/I2C/UART) connect to standard audio codecs and external DAC/ADC devices. With 128 KB of Flash, coefficient tables and short code sequences reside on-chip, and 16 KB of SRAM provides audio block buffering. Unlike an audio-dedicated DSP, the DSC also integrates the system-control role - button scanning, display driving, and housekeeping - eliminating a second MCU in cost-sensitive audio products such as mixers, effect pedals, and PA controllers.
Recommended
Industrial Automation Nodes
In factory automation, the DSPIC33FJ128GP310A-I serves as an intelligent sensor/actuator node combining control I/O with communication. UART, SPI, and I2C interfaces link to field transceivers, EEPROM, and displays; input-capture channels timestamp encoder pulses; and the 12-bit ADC digitizes analog process variables at up to industrial sampling rates. The 40 MIPS budget leaves room for protocol stacks and local control logic simultaneously, and the industrial -40C to +85C rating tolerates panel and machine-mounted environments. Flash self-programming supports parameter storage and field updates without external nonvolatile memory in many designs, reducing BOM cost and board area on dense I/O cards.
Recommended
Sensor Fusion and Data Acquisition
Multi-channel data acquisition benefits from the dual-ADC infrastructure of the dsPIC33FJ GP310A, which can sample multiple 12-bit channels with flexible scan and alternate modes under timer or PWM triggering for deterministic sampling intervals. On-chip DSP instructions perform decimation, offset correction, and windowed analysis locally, streaming reduced-rate results over UART or SPI instead of raw data - cutting bus bandwidth and host load. The 16 KB SRAM buffers acquisition blocks, and 40 MIPS ensures loop determinism even with filtering active. Applications include condition monitoring, portable instrumentation, and multi-sensor industrial telemetry where -40C to +85C operation and single-chip integration shorten qualification cycles.
Recommended
Embedded Control with Field Upgradability
Products requiring long service life and firmware updates in the field - charge controllers, irrigation controls, HVAC boards - are well served by the DSPIC33FJ128GP310A-I. Its Flash self-write capability lets application code update parameters or even its own program image through an in-field bootloader over UART, cutting service costs. The 128 KB Flash provides dual-image space strategies for safe updates, 40 MIPS keeps application headroom generous for future feature additions, and the standard Microchip in-circuit serial programming interface supports production programming on the same footprint used by other dsPIC33FJ 100-pin family members - enabling one PCB design with multiple memory-tier BOM options.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33FJ128GP310A-I — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33FJ128GP310-I/PT | DSPIC33FJ64GP310A-I/PT | DSPIC33FJ256GP310A-I/PT | DSPIC33FJ128GP710A-I/PT | DSPIC33FJ128MC510A-I/PT |
|---|---|---|---|---|---|---|
| Package | TQFP-100 (14x14 mm, PT) | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Flash Memory | 128 KB | 128 KB | 64 KB | 256 KB | 128 KB | 128 KB |
| Max CPU Speed | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS |
| Silicon Stepping | A-step (errata-corrected) | Original stepping (carries earlier errata) | A-step | A-step | A-step | A-step |
| Peripheral Branch | GP (general purpose / audio-capable) | GP - same | GP - same | GP - same | GP710 branch - different peripheral mix | MC (motor control) branch |
| Operating Temperature | -40C to +85C (I) | -40C to +85C (I) | -40C to +85C (I) | -40C to +85C (I) | -40C to +85C (I) | -40C to +85C (I) |
| Firmware Compatibility | Baseline | Identical (verified fully replaceable per FindIC) | Identical, check code size fits 64 KB | Identical | Peripheral re-verification required | Peripheral re-verification required |
Key Differentiators
- A-step silicon errata correction (vs DSPIC33FJ128GP310-I/PT)
- Memory tier flexibility on one footprint (vs DSPIC33FJ64GP310A-I/PT)
- GP (audio-capable) peripheral branch (vs DSPIC33FJ128MC510A-I/PT)
Design Notes
The dsPIC33FJ core runs from a 3.0V-3.6V rail; at 40 MIPS the core current concentrates transient demand on the supply. Place a low-ESR 0.1uF ceramic capacitor at every VDD/VSS pin pair around the 100-pin TQFP, plus bulk 4.7uF-10uF near the corner supply entries. Verify worst-case device current from the manufacturer datasheet electrical characteristics table (values vary with operating frequency and oscillator configuration) before sizing the 3.3V regulator - do not rely on typical values alone.
Silicon stepping matters: the DSPIC33FJ128GP310A ('A' revision) corrects documented errata of the original dsPIC33FJ128GP310. Before adopting the original-step part as a cost-saving alternate, download the relevant silicon errata sheet from Microchip and check whether your firmware uses affected peripherals or instruction sequences. Also note that part suffix encodes temperature (-40C to +85C for 'I') and package (PT = TQFP-100) - mixing suffixes in one BOM can silently change qualification coverage.
On a 100-pin TQFP, fast digital edges from the 40 MIPS core share the package with the 12-bit ADC inputs. Keep analog traces routed away from oscillator and communication clock lines, use a solid ground plane under the ADC section, and filter analog reference inputs with RC networks sized for your sampling rate. Configure unused I/O as outputs driving low or inputs with pull-downs in firmware to prevent floating-pin EMI and excess current - a documented best practice in Microchip dsPIC33F family application notes.
Design the footprint for the full family, not just this part: the 100-pin TQFP-100 (14x14 mm, 0.5 mm pitch) footprint accepts DSPIC33FJ64GP310A, DSPIC33FJ256GP310A, GP710A, and MC510A variants, enabling a single PCB with memory-tier and peripheral-branch BOM options for supply resilience. Expose programming/debug pads (ICSP signals) on every production board even if not used in the end product - in-field firmware updates via Flash self-write depend on access to these pins.
Compliance Information
Compliance data for this exact ordering code was not present in the verified web data; the source description (adatasheet) references an automotive-adjacent 3.3V 100-pin TQFP listing, but per-item RoHS/REACH/lead-free must be confirmed on the Microchip product page. Not positioned as an AEC-Q100 automotive part; use Microchip automotive-qualified variants where qualification is required.
