DSPIC33FJ128MC506AT-I/PT - 16-bit 40 MIPS DSC | Microchip
MPN: DSPIC33FJ128MC506AT-I/PT ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6.48 | $6.48 |
| 10 | $6.15 | $61.50 |
| 100 | $5.8 | $580.00 |
| 500 | $5.45 | $2,725.00 |
| 1,000 | $5.1 | $5,100.00 |
DSPIC33FJ128MC506AT-I/PT Overview
A digital signal controller combines the compute throughput of a DSP core with the peripheral integration and interrupt flexibility of a microcontroller, occupying the middle of the embedded processing hierarchy between general-purpose MCUs and dedicated DSPs. The dsPIC33F family pairs its 16-bit CPU with a fixed-point DSP engine, making it a power-management IC-level single-chip solution for closed-loop control systems.
Key features include the 40 MIPS dsPIC33F core, 128KB self-programmable FLASH with ECC-style erase/write endurance, 8 DMA channels that move data without CPU intervention, four serial I/O ports (UART, SPI, I2C), and nine timers. The industrial (I) temperature grade covers -40C to +85C for demanding environments.
The architecture integrates the DSP engine (17-bit x 17-bit multiplier, 40-bit accumulator, dual fetch) with motor-control peripherals such as the PWM module and quadrature encoder interface inputs, plus a fast 12-bit ADC. The 64-pin TQFP 10x10 mm footprint provides enough I/O to drive three-phase inverters and communicate over multiple serial buses simultaneously.
Typical applications include brushless DC (BLDC) motor control, single- and 3-phase induction motor drives, switched reluctance motor systems, universal power-factor-corrected power supplies, and digital power conversion, all explicitly listed as target uses on Microchip's dsPIC33FJ128MC506A product page.
Design consideration: the 3.0V to 3.6V supply window means the part should be powered from a regulated 3.3V rail; observe the 100 nF decoupling per VDD pin practice from the Microchip datasheet and keep the analog supply isolated for ADC accuracy.
This page synthesizes distributor pricing, drop-in alternatives, pinout data, and practical design notes not found on any single manufacturer or distributor page.
Drop-in alternatives for DSPIC33FJ128MC506AT-I/PT — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33FJ128MC506AT-I/PT (same form factor and footprint) — differing in Core Architecture, Package, Timers, ADC, Data RAM.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33FJ128MC506A-I/PT
✅ Drop-In✓ In Stock
$3.2 / Unit
View Datasheet →DSPIC33FJ128MC506AT-E/PT
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33FJ128MC506-I/PT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ256MC506AT-I/PT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ64MC506AT-I/PT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ128MC506AT-I/PT Maximum Ratings & Electrical Characteristics
| Core Architecture | 16-bit dsPIC33F |
| Maximum CPU Speed | 40 MIPS |
| Program Memory Size | 128KB (128K x 8) FLASH |
| RAM Size | 8KB |
| Supply Voltage Range | 3 V to 3.6 V |
| Operating Temperature Range | -40C to +85C (Industrial) |
| Package | 64-TQFP (10x10 mm) |
| Mounting Type | Surface Mount |
| DMA Channels | 8 |
| Timers | 9 |
| Serial I/O Ports | 4 |
| Series | dsPIC33FJ128MC506AT |
| Core Type | Fixed-point DSP |
| Product Type | Digital Signal Controller (DSC) |
| RoHS Status | Compliant |
| Interface Types | I2C, SPI, UART |
DSPIC33FJ128MC506AT-I/PT Pin Configuration
| Pin 1 | MCLR — Master clear reset input |
| Pin 2 | AN0/VREF+/RB0 — Analog input 0 / positive voltage reference / port B |
| Pin 3 | AN1/VREF-/RB1 — Analog input 1 / negative voltage reference / port B |
| Pin 4 | AN2/SS1/RB2 — Analog input 2 / SPI slave select / port B |
| Pin 5 | AN3/INDX/RB3 — Analog input 3 / QEI index / port B |
| Pin 6 | AN4/QEA/RB4 — Analog input 4 / QEI phase A / port B |
| Pin 7 | AN5/QEB/RB5 — Analog input 5 / QEI phase B / port B |
| Pin 8 | AN6/OCFA/RB6 — Analog input 6 / PWM fault A / port B |
| Pin 9 | AN7/OCFB/RB7 — Analog input 7 / PWM fault B / port B |
| Pin 10 | VSS — Ground reference |
| Pin 11 | VDD — Power supply (3.0V to 3.6V) |
| Pin 12 | AN8/PGD/RB8 — Analog input 8 / programming data / port B |
| Pin 13 | AN9/PGC/RB9 — Analog input 9 / programming clock / port B |
| Pin 14 | AN10/TMS/RB10 — Analog input 10 / JTAG TMS / port B |
| Pin 15 | AN11/TCK/RB11 — Analog input 11 / JTAG TCK / port B |
| Pin 16 | AN12/RB12 — Analog input 12 / port B |
| Pin 17 | AN13/RB13 — Analog input 13 / port B |
| Pin 18 | AN14/RB14 — Analog input 14 / port B |
| Pin 19 | AN15/OCIC/RB15 — Analog input 15 / PWM fault C / port B |
| Pin 20 | AVDD — Analog power supply |
| Pin 21 | AVSS — Analog ground |
| Pin 22 | OSC1/CLKI — Oscillator crystal input / external clock input |
| Pin 23 | OSC2/CLKO/RC15 — Oscillator crystal output / clock output / port C |
| Pin 24 | RC13 — Port C I/O / secondary oscillator input |
| Pin 25 | RC14 — Port C I/O / secondary oscillator output |
| Pin 26 | RD0 — Port D I/O / PWM output |
| Pin 27 | RD1 — Port D I/O / PWM output |
| Pin 28 | RD2 — Port D I/O / PWM output |
| Pin 29 | RD3 — Port D I/O / PWM output |
| Pin 30 | VDD — Power supply |
| Pin 31 | VSS — Ground reference |
| Pin 32 | RF2/U1RX — Port F I/O / UART1 receive |
| Pin 33 | RF3/U1TX — Port F I/O / UART1 transmit |
| Pin 34 | RF4/U2RX — Port F I/O / UART2 receive |
| Pin 35 | RF5/U2TX — Port F I/O / UART2 transmit |
| Pin 36 | RF6 — Port F I/O |
| Pin 37 | RF7 — Port F I/O |
| Pin 38 | VDD — Power supply |
| Pin 39 | VSS — Ground reference |
| Pin 40 | RD4 — Port D I/O / PWM output |
| Pin 41 | RD5 — Port D I/O / PWM output |
| Pin 42 | RD6 — Port D I/O / PWM output |
| Pin 43 | RD7 — Port D I/O / PWM output |
| Pin 44 | RF8 — Port F I/O / UART3 |
| Pin 45 | RF12 — Port F I/O / SPI port I/O |
| Pin 46 | RF13 — Port F I/O / SPI port I/O |
| Pin 47 | VDD — Power supply |
| Pin 48 | VSS — Ground reference |
| Pin 49 | RC1/T2CK — Port C I/O / Timer 2 external clock |
| Pin 50 | RC2/T3CK — Port C I/O / Timer 3 external clock |
| Pin 51 | RC3/T4CK — Port C I/O / Timer 4 external clock |
| Pin 52 | RC4/T5CK — Port C I/O / Timer 5 external clock |
| Pin 53 | RG6/SCK2 — Port G I/O / SPI2 clock |
| Pin 54 | RG7/SDI2 — Port G I/O / SPI2 data in |
| Pin 55 | RG8/SDO2 — Port G I/O / SPI2 data out |
| Pin 56 | RG9/SS2 — Port G I/O / SPI2 slave select |
| Pin 57 | VDD — Power supply |
| Pin 58 | VSS — Ground reference |
| Pin 59 | RD8 — Port D I/O / PWM output |
| Pin 60 | RD9 — Port D I/O / PWM output |
| Pin 61 | RD10 — Port D I/O / PWM output |
| Pin 62 | RD11 — Port D I/O / PWM output |
| Pin 63 | RD12 — Port D I/O |
| Pin 64 | RD13 — Port D I/O |
Typical Applications
DSPIC33FJ128MC506AT-I/PT is suitable for 6 applications: Brushless DC (BLDC) Motor Control, Single- and 3-Phase Induction Motor Drives, Switched Reluctance Motor (SRM) Control, Digital Power Conversion and PFC, Industrial Automation and Robotics, Embedded Signal Acquisition Systems.
Brushless DC (BLDC) Motor Control
Microchip explicitly targets BLDC control on the dsPIC33FJ128MC506A family. The DSPIC33FJ128MC506AT-I/PT combines its 40 MIPS DSP engine with a motor-control PWM module generating complementary, dead-time-controlled outputs for three-phase inverters, while the 12-bit ADC samples phase currents within a single PWM cycle for closed-loop commutation. Quadrature encoder interface inputs (QEA/QEB) on PORTB provide position feedback for FOC or trapezoidal schemes. The 8 DMA channels stream ADC results to RAM without CPU intervention, keeping loop overhead low. Place the controller between gate-driver inputs (e.g., a 3.3V-to-5V level interface) and the current-sense amplifier outputs; its 3.0V-3.6V rail must be well regulated to preserve ADC accuracy across the -40C to +85C industrial range.
Recommended
Single- and 3-Phase Induction Motor Drives
Per Microchip's product page, the dsPIC33FJ128MC506A family supports single- and 3-phase induction motor applications. The DSPIC33FJ128MC506AT-I/PT's fixed-point DSP engine with 17x17-bit multiplier executes V/Hz and sensorless field-oriented algorithms at 40 MIPS, while the PWM module produces the multi-channel, dead-time-inserted waveform set needed for IGBT or MOSFET bridges. Four serial ports let the controller attach an RS-485/Modbus link, an HMI, and a debug console simultaneously, and the nine timers cover carrier generation, fault protection, and task scheduling. Typical deployment is an industrial drive board where the DSC reads DC-bus voltage and phase currents via the 12-bit ADC, computes the control loop, and trips outputs on fault conditions within microseconds.
Recommended
Switched Reluctance Motor (SRM) Control
Switched reluctance drives require precise phase-current profiling and rapid commutation, which the DSPIC33FJ128MC506AT-I/PT handles through its 40 MIPS core, multiple PWM channels, and fast 12-bit ADC sampling on up to 16 analog inputs. Microchip lists SRM among the target applications of the dsPIC33FJ128MC506A family. The 8 DMA channels continuously transfer current samples to RAM, and the DSP engine's dual-fetch architecture sustains per-phase control loops at high switching frequency. Because SRM control is heavily interrupt-driven, the deterministic 16-bit core and nine timers of the dsPIC33F architecture let engineers phase-lock commutation events to rotor position from encoder or resolver-derived signals without external logic, consolidating the whole drive controller into this single 64-TQFP device.
Recommended
Digital Power Conversion and PFC
Universal-input power supplies and power-factor-corrected stages need high-speed current shaping loops that the DSPIC33FJ128MC506AT-I/PT delivers with its 40 MIPS DSP engine and 12-bit ADC triggering directly from the PWM module. Average-current-mode PFC, LLC, and phase-shifted full-bridge algorithms fit within the 128KB FLASH with room for communication and housekeeping firmware. The four serial ports enable PMBus/UART supervisory links, and the 8 DMA channels offload telemetry logging. In a typical design the DSC senses inductor current and bus voltage each switching cycle, computes the duty correction, and updates the PWM comparators - a digital control rate impossible on general-purpose MCUs. The -40C to +85C industrial grade suits telecom rectifier and solar micro-inverter environments.
Recommended
Industrial Automation and Robotics
Servo axes, conveyors, and robotic joints integrate the DSPIC33FJ128MC506AT-I/PT as the motion controller thanks to its quadrature encoder interface, 40 MIPS control throughput, and 64 I/O-capable pins in the 10x10 mm TQFP. The DSP engine runs PID or FOC loops at fixed sample rates while the UART, SPI, and I2C ports connect drives, sensors, and a fieldbus gateway simultaneously. Nine timers and 8 DMA channels schedule multi-axis coordination without CPU overload, and the 128KB FLASH stores motion profiles, parameter tables, and field-updatable firmware. Its 3.0V-3.6V supply allows direct interfacing with 3.3V logic and isolated transceivers, while the -40C to +85C rating covers unconditioned factory-floor cabinets commonly encountered in automation installations.
Recommended
Embedded Signal Acquisition Systems
The DSPIC33FJ128MC506AT-I/PT doubles as a DSP-class acquisition front end: its 12-bit ADC with multiple sample-and-hold inputs digitizes up to 16 channels on PORTB, and the fixed-point DSP engine executes FFT, filtering, and RMS computation in real time at 40 MIPS. The 8 DMA channels stream conversion results into the 8KB RAM buffer while the UART or SPI port forwards processed data to a host, all within the single 64-TQFP. Typical products include industrial condition-monitoring nodes, power-quality analyzers, and sensor hubs where the -40C to +85C industrial rating and 3.0V-3.6V supply simplify integration. The 128KB FLASH holds both the signal-processing firmware and communication protocol stack with headroom for OTA field updates.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33FJ128MC506AT-I/PT — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33FJ128MC506A-I/PT | DSPIC33FJ128MC506AT-E/PT | DSPIC33FJ256MC506AT-I/PT | DSPIC33FJ64MC506AT-I/PT |
|---|---|---|---|---|---|
| Package | 64-TQFP (10x10 mm) | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| CPU Speed | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS |
| FLASH Memory | 128KB | 128KB | 128KB | 256KB | 64KB |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +125C | -40C to +85C | -40C to +85C |
| Supply Voltage | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V |
| DMA Channels / Serial Ports | 8 DMA / 4 serial | 8 DMA / 4 serial | 8 DMA / 4 serial | 8 DMA / 4 serial | 8 DMA / 4 serial |
Key Differentiators
- Full 128KB FLASH with maximum peripheral set in the 506 family (vs DSPIC33FJ64MC506AT-I/PT)
- Extended temperature option for hot environments (vs DSPIC33FJ128MC506AT-E/PT)
- A-revision silicon eliminates early family errata (vs DSPIC33FJ128MC506-I/PT)
Design Notes
The DSPIC33FJ128MC506AT-I/PT requires a regulated 3.0V-3.6V rail; design for a 3.3V LDO or buck output with less than 2% ripple. Place 100 nF ceramic decoupling capacitors at every VDD pin (pins 11, 30, 38, 47, 57) plus a 4.7-10 uF bulk capacitor near pin 11. Decouple AVDD (pin 20) separately with 100 nF and an optional ferrite bead from the digital rail to preserve 12-bit ADC accuracy. Estimated: at 40 MIPS with typical I/O loading, core current is in the tens of mA range - verify exact figure in the Microchip datasheet electrical characteristics table before finalizing supply budget.
For motor-control layouts, keep the QEA/QEB/INDX encoder traces (pins 5-7) short and away from PWM outputs (RD0-RD3, RD8-RD11) to prevent false QEI counts from switching edges. Route AN0-AN15 analog traces as a shielded group to AVSS. Use the crystal on OSC1/OSC2 (pins 22-23) with load capacitors per the crystal vendor spec and keep the loop under 10 mm. Follow the Microchip 64-TQFP footprint land pattern exactly - the 10x10 mm body with 0.5 mm pitch leaves little routing escape margin, so fan out power pins first.
Three common pitfalls: (1) Confusing the -I (industrial, +85C) and -E (extended, +125C) grades - the AT-E/PT is the drop-in choice for hot enclosures, and substituting the -I grade voids thermal margin. (2) Mixing the non-A and A silicon revisions - early dsPIC33FJ errata items were corrected in the A revision; always compile with current device support files. (3) Forgetting that MCLR (pin 1) needs a pull-up (typically 10k to VDD) and is used for In-Circuit Serial Programming - reserve header access to PGD (pin 12) and PGC (pin 13) on the PCB for field programming.
Compliance Information
RoHS compliance indicated by distributor listings (LCSC/DigiKey). REACH, halogen-free and conflict-minerals status not stated in provided data - verify on Microchip's product compliance page.
