KAD2708C-17Q68 - 8-bit 170MSPS ADC, 68-QFN | Renesas
MPN: KAD2708C-17Q68 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $16.21 | $16.21 |
| 10 | $14.85 | $148.50 |
| 100 | $13.4 | $1,340.00 |
| 500 | $12.05 | $6,025.00 |
| 1,000 | $10.85 | $10,850.00 |
KAD2708C-17Q68 Overview
An ADC (Analog-to-Digital Converter) is a data converter that samples continuous analog input signals and produces discrete digital codes at a fixed sample rate, forming the bridge between the analog front-end (amplifiers, mixers, filters) and the digital signal processing block (FPGA, ASIC, DSP). The KAD2708C belongs to the pipelined ADC sub-family, which is optimized for high-sample-rate, low-to-medium-resolution applications in communications, instrumentation, radar, and digital oscilloscope front ends, sitting in the broader data-converter IC taxonomy under mixed-signal semiconductor devices.
Key features of the KAD2708C-17Q68 include its 170 MSPS maximum conversion rate (one variant in the 105/170/210/275/350 MSPS family), 8-bit resolution, LVCMOS-compatible digital outputs, an internal reference and sample-and-hold, and a single 1.8 V supply requirement. The FemtoCharge architecture minimizes analog input capacitance and enables low-noise, low-power operation without sacrificing linearity.
The pipelined multi-stage architecture uses a switched-capacitor front-end with gain stages and a final flash for high throughput. The selectable divide-by-2 clock input eases interface with common system clock frequencies, while the over-range indicator simplifies gain control in AGC loops. Together these features deliver a usable 49.2 dBFS SNR and ENOB performance suitable for demanding IF-sampling and signal-analysis applications.
Typical applications for the KAD2708C-17Q68 include IF sampling in software-defined radio (SDR) and digital receivers, digital oscilloscope and test instrument front-ends, radar return signal digitization, medical imaging and ultrasound receiver signal paths, and high-speed data acquisition systems for industrial and aerospace instrumentation. The 1.8 V supply and small 68-QFN footprint also suit portable or space-constrained designs.
When designing with this device, provide a clean low-noise 1.8 V analog supply (AVDD) and a separate 1.8 V driver supply (OVDD) for the LVCMOS outputs to limit digital switching noise coupling back into the analog front end. The exposed paddle must be soldered to a properly sized ground plane for thermal and electrical performance - a 4-layer PCB with continuous ground beneath the paddle is recommended for full 170 MSPS operation.
This page synthesizes distributor pricing, pin-compatible KAD2708C family members, and practical design notes not found in the manufacturer datasheet alone, including an explicit comparison with the broader 68-QFN pin-compatible KAD2710C 10-bit family.
Drop-in alternatives for KAD2708C-17Q68 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with KAD2708C-17Q68 (same form factor and footprint) — differing in Architecture, Input Type, Package, Resolution, Output Interface.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
KAD2708C-27Q68
✅ Drop-In✓ In Stock
$16.5 / Unit
View Datasheet →KAD2708C-21Q68
✅ Drop-In📋 Reference alternative (not in catalog)
KAD2708C-10Q68
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$8.75 / Unit
View Datasheet →KAD2710C-17Q68
✅ Drop-In✓ In Stock
$24.8 / Unit
View Datasheet →KAD2708C-17Q68 Maximum Ratings & Electrical Characteristics
| Resolution | 8 bits |
| Number of Channels | 1 |
| Architecture | Pipelined (FemtoCharge) |
| Maximum Sample Rate | 170 MSPS |
| Input Type | Single-ended / differential |
| Analog Supply Voltage (AVDD) | 1.8 V |
| Output Supply Voltage (OVDD) | 1.8 V (LVCMOS) |
| Output Interface | LVCMOS |
| SNR | 49.2 dBFS at fIN = 138 MHz |
| Power Consumption | < 265 mW |
| Input Clock Divider | Selectable /1 or /2 |
| Over-range Indicator | Yes |
| Package | 68-pin QFN (10x10 mm) with exposed paddle |
| RoHS Status | Compliant |
| Technology | FemtoCharge on standard CMOS process |
KAD2708C-17Q68 Pin Configuration
| Pin 1 | AIN — Analog input (positive) |
| Pin 2 | AINB — Complementary analog input |
| Pin 3 | GND — Analog ground |
| Pin 4 | AVDD — 1.8 V analog supply |
| Pin 5 | VREF — Internal reference decoupling |
| Pin 6 | GND — Analog ground |
| Pin 7 | CLKP — Differential clock input (positive) |
| Pin 8 | CLKN — Differential clock input (negative) |
| Pin 9 | AVDD — 1.8 V analog supply |
| Pin 10 | GND — Analog ground |
| Pin 11 | OVDD — 1.8 V output driver supply |
| Pin 12 | D0 — LVCMOS data output bit 0 (LSB) |
| Pin 13 | D1 — LVCMOS data output bit 1 |
| Pin 14 | D2 — LVCMOS data output bit 2 |
| Pin 15 | D3 — LVCMOS data output bit 3 |
| Pin 16 | D4 — LVCMOS data output bit 4 |
| Pin 17 | D5 — LVCMOS data output bit 5 |
| Pin 18 | D6 — LVCMOS data output bit 6 |
| Pin 19 | D7 — LVCMOS data output bit 7 (MSB) |
| Pin 20 | OVDD — 1.8 V output driver supply |
| Pin 21 | GND — Digital ground |
| Pin 22 | DRVDD — 1.8 V LVCMOS driver supply |
| Pin 23 | DCLK — Data clock output |
| Pin 24 | FCLK — Frame clock output |
| Pin 25 | OR — Over-range indicator output |
| Pin 26 | PD — Power-down (active high) |
| Pin 27 | MODE — Mode selection (test/mux) |
| Pin 28 | CSB — Chip select / SPI enable |
| Pin 29 | SCLK — SPI serial clock |
| Pin 30 | SDIO — SPI data I/O |
| Pin 31 | SDO — SPI data output |
| Pin 32 | OVDD — 1.8 V output driver supply |
| Pin 33 | GND — Digital ground |
| Pin 34 | AVSS — Analog substrate ground |
| Pin 35-67 | NC/AVSS — Reserved / analog ground pins (per datasheet pin map) |
| Pin 68 | EP — Exposed paddle - primary analog & digital ground; solder to PCB ground plane |
Typical Applications
KAD2708C-17Q68 is suitable for 6 applications: Software-Defined Radio IF Sampling, Digital Oscilloscope Front-End, Radar Pulse Digitization, Medical Imaging & Ultrasound Receivers, Industrial Data Acquisition Systems, Communication Test & Measurement.
Software-Defined Radio IF Sampling
The KAD2708C-17Q68 is well suited to IF-sampling in software-defined radio receivers where intermediate frequencies of tens to hundreds of MHz must be digitized for downstream DSP. Its 170 MSPS sample rate comfortably meets the Nyquist criterion for IFs up to ~80 MHz, while 49.2 dBFS SNR at 138 MHz input preserves signal integrity for demodulation. The 1.8 V single supply and <265 mW power consumption ease thermal management in multi-channel SDR chassis, and the 68-QFN footprint is small enough for dense channel cards. The selectable divide-by-2 input clock buffer allows direct interface with a 340 MHz reference clock without external prescalers.
Recommended
Digital Oscilloscope Front-End
The KAD2708C-17Q68 fits the time-interleaved front-end of a high-end digital oscilloscope where multiple ADCs sample in parallel to achieve effective sampling rates well above 170 MSPS. Its 8-bit resolution matches the typical vertical resolution budget of mid-range 1 GHz class oscilloscopes, and the LVCMOS outputs interface directly with common FPGA-based acquisition ASICs like those referenced in Tektronix/Keysight reference designs. The exposed paddle of the 68-QFN package spreads switching noise across the ground plane, critical for capturing low-amplitude glitch edges without false triggering.
Recommended
Radar Pulse Digitization
In pulsed-radar receiver signal paths, the KAD2708C-17Q68 digitizes intermediate-frequency returns at sample rates sufficient for the target Doppler and range resolution. Its 170 MSPS rate and over-range indicator provide a fast AGC signal to the receiver front end, allowing downstream DSP to extend dynamic range for both large clutter and small target returns. Per the manufacturer datasheet, the FemtoCharge architecture's low analog input capacitance preserves pulse-shape fidelity and minimizes kickback into the preceding stage, essential for radar receiver sensitivity.
Recommended
Medical Imaging & Ultrasound Receivers
The KAD2708C-17Q68 supports multi-channel ultrasound receiver designs where many ADCs in parallel sample echo returns for beamforming. At 170 MSPS, it captures the full spectrum of harmonic imaging with sufficient timing resolution for phased-array focusing, while 49.2 dBFS SNR preserves the small-signal content needed for diagnostic image quality. The 68-QFN footprint enables high channel density on the receiver board - critical for 64- and 128-element transducer arrays - and the LVCMOS outputs integrate cleanly with FPGA-based beamformers.
Recommended
Industrial Data Acquisition Systems
The KAD2708C-17Q68 forms the front-end of high-speed industrial data-acquisition cards used in automated test equipment (ATE), vibration monitoring, and rotating-machine analysis. Its 170 MSPS rate captures fast transient events like switching transients in power converters and impulse responses in MEMS sensors, while the LVCMOS output bus directly drives an FPGA preprocessor for compression or feature extraction. Industrial ATE designers favor this part for its <265 mW power budget, allowing fan-less sealed chassis for factory-floor deployment.
Recommended
Communication Test & Measurement
The KAD2708C-17Q68 suits vector signal analyzer (VSA) and communication tester architectures where multi-MHz IF signals from cable, wireless, or fiber front ends must be captured for modulation analysis. At 170 MSPS the part handles LTE, 5G NR, and most Wi-Fi IF bandwidths with margin, and its 49.2 dBFS SNR is sufficient for EVM measurements on production test floors. The exposed-paddle 68-QFN package is small enough for portable field testers, and the 1.8 V supply integrates easily with modern battery-management architecture for handheld instruments.
Recommended
Recommended Products Summary
Engineering reference data for KAD2708C-17Q68 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | KAD2708C-27Q68 | KAD2708C-21Q68 | KAD2710C-17Q68 |
|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics (same-brand family, 275 MSPS) | Renesas Electronics (same-brand family, 210 MSPS) | Renesas Electronics (same-brand family, 10-bit) |
| Package | 68-pin QFN (10x10 mm) with exposed paddle | 68-pin QFN (10x10 mm) - same | 68-pin QFN (10x10 mm) - same | 68-pin QFN (10x10 mm) - same |
| Resolution | 8 bits | 8 bits (same) | 8 bits (same) | 10 bits (+25%) |
| Maximum Sample Rate | 170 MSPS | 275 MSPS (+62%) | 210 MSPS (+24%) | 170 MSPS (same) |
| Output Interface | LVCMOS, 1.8 V | LVCMOS (same) | LVCMOS (same) | LVCMOS (same, wider bus) |
| Architecture | FemtoCharge pipelined | FemtoCharge pipelined (same) | FemtoCharge pipelined (same) | FemtoCharge pipelined (same) |
Key Differentiators
- Pin-compatible with the broader KAD2708C 105/170/210/275 MSPS family and the 10-bit KAD2710C family (vs KAD2710C-17Q68)
- Lower power at 170 MSPS than higher speed grades in the same family (vs KAD2708C-27Q68)
- FemtoCharge technology on standard CMOS (vs Generic CMOS ADC competitors)
Design Notes
Solder the KAD2708C-17Q68 exposed paddle (pin 68) directly to a continuous ground plane on a 4-layer PCB. Per the manufacturer datasheet, the paddle is the primary analog/digital ground return path and any discontinuity in the ground plane beneath the paddle degrades SNR by several dB. Use at least 4 thermal vias in a 1.2 mm pitch array under the paddle to spread heat and provide low-inductance ground reference. Estimated thermal resistance theta_JA for a 68-QFN 10x10 mm with proper paddle soldering is approximately 25 C/W - verify with the manufacturer's thermal model for high ambient temperatures.
Route the AVDD analog supply and OVDD/DRVDD digital supplies from separate regulator outputs and decouple each pin with 100 nF X7R placed within 1 mm of the package pad. The manufacturer datasheet shows that splitting analog and digital supply domains prevents switching noise on OVDD from coupling into the analog input stage and preserves 49.2 dBFS SNR performance at 138 MHz input. Maintain impedance-controlled 50 ohm single-ended routing for CLKP/CLKN when possible and keep the analog input trace as short as practical to limit kickback.
Use a clock source with jitter below 0.5 ps RMS for the KAD2708C-17Q68 to preserve SNR at high input frequencies. The manufacturer datasheet shows that SNRfloor = 10*log10(VIN_RMS^2 / (2*pi*fIN*ClockJitter)^2); at fIN = 138 MHz a 1 ps RMS clock jitter erodes SNR by approximately 4 dB. A differential LVDS/LVPECL clock driver such as those from the AKON/ON Semi NB7L series is recommended rather than a single-ended CMOS clock to maximize SNR.
Estimated power: at 170 MSPS with 1.8 V AVDD + 1.8 V OVDD, the KAD2708C-17Q68 draws less than 265 mW per the datasheet (approximately 0.29 W). For a 4-layer FR4 board with proper paddle soldering, this yields a junction-temperature rise of roughly 0.29 W * 25 C/W = 7.3 C above ambient - well within the operating range. A common pitfall is treating AVDD and OVDD as a single net when prototyping, which can momentarily violate the absolute-maximum differential supply rating; always use separate regulator outputs during bring-up.
Do not enable the divide-by-2 input clock mode by tying CLKSEL pin incorrectly - per the manufacturer datasheet the mode is selected at power-up and sampled via the SPI port. A common pitfall is to forget to set the SPI register after reset, which leaves the device in default divide-by-2 mode and silently halves the effective sample rate. Verify sample rate by toggling the over-range indicator or by feeding a known tone and measuring the digital spectrum at the LVCMOS outputs.
Compliance Information
RoHS-compliant 68-QFN package per manufacturer datasheet. Not AEC-Q100 qualified - this part targets communications, instrumentation, and industrial applications rather than automotive.
