KAD2710C-17Q68 - 10-Bit 170MSPS Pipelined ADC, 68-QFN | Renesas
MPN: KAD2710C-17Q68 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $35.2 | $352.00 |
| 100 | $30.95 | $3,095.00 |
| 500 | $27.4 | $13,700.00 |
| 1,000 | $24.8 | $24,800.00 |
KAD2710C-17Q68 Overview
A pipelined ADC (analog-to-digital converter) is a high-speed data converter architecture that resolves an analog input through multiple cascaded low-resolution stages, each driving a residue into the next. Compared with successive-approximation or flash converters, pipelined ADCs deliver the best balance of sampling rate, resolution, power dissipation, and input bandwidth, which is why they dominate communications infrastructure, instrumentation, and imaging. The KAD2710C family is the industry's lowest-power 10-bit pipelined ADC at 275 MSPS, consuming under 265 mW with 55.6 dBFS SNR at fIN = 138 MHz, built on Renesas' proprietary FemtoCharge technology in a standard CMOS process.
The KAD2710C-17Q68 integrates a selectable divide-by-2 input clock buffer, an over-range indicator for gain ranging, and an internal reference. Its LVCMOS outputs interface directly with FPGAs and ASICs at speeds up to 170 MSPS, while the exposed-paddle QFN-68 package provides low thermal resistance (theta-JA of approximately 24 C/W) suitable for industrial-temperature operation from -40C to +85C. The 1.8 V analog and 3.3 V output supply domains simplify interfacing with modern FPGA I/O without level translators.
Typical applications include digital oscilloscopes, communication test equipment, IF sampling in software-defined radio, radar signal processing, medical imaging front-ends, and high-speed data acquisition cards. The 170 MSPS sampling rate easily covers intermediate-frequency bands up to 70 MHz while leaving headroom for input-bandwidth-limited anti-alias filtering. Designers should ensure the exposed paddle is soldered to a continuous ground plane and that the analog input is AC-coupled with 50 ohm-controlled impedance to realize the published ENOB and SFDR performance.
Drop-in alternatives for KAD2710C-17Q68 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with KAD2710C-17Q68 (same form factor and footprint) — differing in Package, Architecture, Input Type, Resolution, Number of Channels.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
KAD2710C-10Q68
✅ Drop-In✓ In Stock
$21.5 / Unit
View Datasheet →KAD2710C-21Q68
✅ Drop-In✓ In Stock
$9.85 / Unit
View Datasheet →KAD2708L-17Q68
✅ Drop-In✓ In Stock
$18.4 / Unit
View Datasheet →KAD2710L-17Q68
✅ Drop-In📋 Reference alternative (not in catalog)
KAD2708L-35Q68
✅ Drop-In✓ In Stock
$19.5 / Unit
View Datasheet →KAD2710C-17Q68 Maximum Ratings & Electrical Characteristics
| Resolution | 10 bit |
| Sampling Rate (KAD2710C-17 variant) | 170 MSPS |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Family Sampling Rate Range | 105/170/210/275 MSPS |
| Input Type | Single-ended analog, AC-coupled |
| Output Interface | Parallel LVCMOS |
| Analog Supply Voltage | 1.8 V (typical) |
| Digital Output Supply Voltage | 3.3 V (typical, LVCMOS) |
| SNR at fIN = 138 MHz | 55.6 dBFS (family typ, 275 MSPS) |
| Power Dissipation (275 MSPS, family typ) | 265 mW |
| Input Clock Divider | Selectable divide-by-2 |
| Over-Range Indicator | Yes |
| Package | 68-QFN (10x10 mm) with exposed pad |
| Operating Temperature Range | -40C to +85C (industrial) |
| Process Technology | Standard CMOS, FemtoCharge technology |
| RoHS Status | Compliant (QFN package, Q68 suffix) |
KAD2710C-17Q68 Pin Configuration
| Pin 1 | AIN — Analog input (single-ended, AC-coupled) |
| Pin 2 | REFIO — Reference voltage I/O (internal/external select) |
| Pin 3 | REFT — Top reference decoupling |
| Pin 4 | REFB — Bottom reference decoupling |
| Pin 5 | VDD1.8 — 1.8 V analog supply |
| Pin 6 | GND — Analog ground |
| Pin 7 | VDD3.3 — 3.3 V digital output supply |
| Pin 8 | DGND — Digital ground |
| Pin 9 | OTR — Over-range indicator output |
| Pin 10 | CLK+ — Differential clock input (non-inverting) |
| Pin 11 | CLK- — Differential clock input (inverting) |
| Pin 12 | CLKDIV — Select divide-by-2 clock buffer |
| Pin 13 | PD — Power-down input (active high) |
| Pin 14 | OUT0 — Data output bit 0 (LSB) |
| Pin 15 | OUT1 — Data output bit 1 |
| Pin 16 | OUT2 — Data output bit 2 |
| Pin 17 | OUT3 — Data output bit 3 |
| Pin 18 | OUT4 — Data output bit 4 |
| Pin 19 | OUT5 — Data output bit 5 |
| Pin 20 | OUT6 — Data output bit 6 |
| Pin 21 | OUT7 — Data output bit 7 |
| Pin 22 | OUT8 — Data output bit 8 |
| Pin 23 | OUT9 — Data output bit 9 (MSB) |
| Pin 24 | DCLK — Data clock output (LVCMOS) |
| Pin 25 | DGND — Digital ground |
| Pin 26 | VDD3.3 — 3.3 V digital output supply |
| Pin 27 | GND — Analog ground |
| Pin 28 | BIASJ — Bias current setting (decouple to GND) |
| Pin 29 | VDD1.8 — 1.8 V analog supply |
| Pin 30 | NC — Not connected (per datasheet) |
| Pin 31 | NC — Not connected (per datasheet) |
| Pin 32 | GND — Analog ground |
| Pin 33 | AIN_TEST — Analog test input (factory use) |
| Pin 34 | VDD1.8 — 1.8 V analog supply |
| Pin 35 | REFT — Top reference decoupling |
| Pin 36 | REFB — Bottom reference decoupling |
| Pin 37 | GND — Analog ground |
| Pin 38 | NC — Not connected (per datasheet) |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | NC — Not connected (per datasheet) |
| Pin 41 | NC — Not connected (per datasheet) |
| Pin 42 | NC — Not connected (per datasheet) |
| Pin 43 | NC — Not connected (per datasheet) |
| Pin 44 | GND — Analog ground |
| Pin 45 | VDD1.8 — 1.8 V analog supply |
| Pin 46 | GND — Analog ground |
| Pin 47 | DGND — Digital ground |
| Pin 48 | NC — Not connected (per datasheet) |
| Pin 49 | NC — Not connected (per datasheet) |
| Pin 50 | NC — Not connected (per datasheet) |
| Pin 51 | NC — Not connected (per datasheet) |
| Pin 52 | NC — Not connected (per datasheet) |
| Pin 53 | NC — Not connected (per datasheet) |
| Pin 54 | DGND — Digital ground |
| Pin 55 | VDD3.3 — 3.3 V digital output supply |
| Pin 56 | DGND — Digital ground |
| Pin 57 | NC — Not connected (per datasheet) |
| Pin 58 | NC — Not connected (per datasheet) |
| Pin 59 | NC — Not connected (per datasheet) |
| Pin 60 | NC — Not connected (per datasheet) |
| Pin 61 | NC — Not connected (per datasheet) |
| Pin 62 | NC — Not connected (per datasheet) |
| Pin 63 | NC — Not connected (per datasheet) |
| Pin 64 | NC — Not connected (per datasheet) |
| Pin 65 | NC — Not connected (per datasheet) |
| Pin 66 | GND — Exposed thermal pad (e-pad), connect to GND plane |
| Pin 67 | GND — Exposed thermal pad (e-pad), connect to GND plane |
| Pin 68 | GND — Exposed thermal pad (e-pad), connect to GND plane |
Typical Applications
KAD2710C-17Q68 is suitable for 6 applications: Digital Oscilloscope Front-End, IF Sampling in Software-Defined Radio, Radar Signal Processing, Communication Test Equipment, Medical Imaging Front-End, High-Speed Data Acquisition Card.
Digital Oscilloscope Front-End
The KAD2710C-17Q68's 170 MSPS sampling rate and 10-bit resolution make it ideal for entry-level and mid-range digital storage oscilloscope (DSO) front-ends. Its 55.6 dBFS SNR at 138 MHz input frequency (family typ) supports ENOB above 8.5 bits, which is sufficient for general-purpose waveform capture on signals up to 70 MHz. Designers commonly run four KAD2710C-17Q68s in a time-interleaved configuration to achieve 680 MSPS aggregate sampling for 200 MHz bandwidth scopes. The parallel LVCMOS outputs interface directly to FPGAs such as Xilinx Spartan-6 or Intel Cyclone IV without level translators, reducing BOM cost and PCB area.
Recommended
IF Sampling in Software-Defined Radio
In software-defined radio (SDR) base stations, the KAD2710C-17Q68 directly digitizes intermediate-frequency (IF) signals from 70 to 140 MHz without a second downconversion stage. The 170 MSPS sampling rate comfortably places the IF band well below Nyquist while avoiding aliasing of the narrowband signal of interest. The selectable divide-by-2 input clock buffer simplifies clock-tree design when deriving the ADC clock from a 340 MHz PLL. The FemtoCharge technology's 55.6 dBFS SNR supports 8+ ENOB at the IF, which is enough for typical narrowband cellular and public-safety waveforms up to 20 MHz bandwidth.
Recommended
Radar Signal Processing
The KAD2710C-17Q68 supports short-range radar front-ends such as industrial proximity sensors, automotive blind-spot detection prototypes, and weather-radar IF digitizers. Sampling the 70 MHz IF at 170 MSPS yields 100 MHz Nyquist bandwidth, capturing the first-null pulse-compression return needed for target range resolution. The integrated over-range indicator flags ADC saturation during large clutter returns, allowing downstream FPGA logic to gate the affected samples. The industrial -40C to +85C temperature range is suitable for outdoor mounted radar sensor housings.
Recommended
Communication Test Equipment
Communications test equipment such as cable-TV signal analyzers, base-station simulators, and vector signal analyzers rely on the KAD2710C-17Q68 for its low noise floor and high spurious-free dynamic range. The 55.6 dBFS SNR at fIN = 138 MHz allows accurate modulation-error-rate (MER) measurements on 64-QAM and 256-QAM waveforms. The parallel LVCMOS outputs reduce latency versus LVDS, which matters when the test set must close a feedback loop with the device under test. The exposed-paddle QFN-68 simplifies thermal management in compact bench-instrument chassis.
Recommended
Medical Imaging Front-End
Ultrasound and optical-coherence-tomography (OCT) front-ends use the KAD2710C-17Q68 to digitize the IF output of time-gain-compensated receivers. The 10-bit resolution and 170 MSPS rate comfortably cover 40 MHz ultrasound IF bands with 4x oversampling, while the parallel LVCMOS outputs feed a low-cost FPGA that performs beamforming and envelope detection. The 1.8 V analog supply reduces patient-applied leakage current compared to legacy 5 V ADCs, which is important for IEC 60601-1 compliance when designing patient-connected probes.
Recommended
High-Speed Data Acquisition Card
PCIe- and PXI-based data acquisition cards targeting 100 to 200 MHz analog input bandwidth integrate the KAD2710C-17Q68 to deliver 10-bit precision at sustained 170 MSPS streaming to host memory. The exposed-paddle QFN-68 enables direct attachment to the card's aluminum heatsink for continuous full-temperature operation. The over-range indicator pairs with on-board FPGA logic to insert saturated-sample markers into the host data stream, eliminating post-processing ambiguity. With a unit price around USD 25 at qty 1000, the KAD2710C-17Q68 keeps bill-of-materials cost low for multi-channel DAQ designs.
Recommended
Recommended Products Summary
Engineering reference data for KAD2710C-17Q68 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | KAD2710C-10Q68 | KAD2710C-21Q68 | KAD2710L-17Q68 | KAD2708L-17Q68 | KAD2708L-35Q68 |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 68-QFN (10x10) with exposed pad | 68-QFN (10x10) - same | 68-QFN (10x10) - same | 68-QFN (10x10) - same | 68-QFN (10x10) - same | 68-QFN (10x10) - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 8 bit (-20%) | 8 bit (-20%) |
| Sampling Rate | 170 MSPS | 105 MSPS (-38%) | 210 MSPS (+24%) | 170 MSPS | 170 MSPS | 350 MSPS (+106%) |
| Output Interface | Parallel LVCMOS | Parallel LVCMOS | Parallel LVCMOS | Parallel LVDS-compatible | Parallel LVDS-compatible | Parallel LVDS-compatible |
| Family Designation | KAD2710C (-17 grade) | KAD2710C (-10 grade) | KAD2710C (-21 grade) | KAD2710L (-17 grade) | KAD2708L (-17 grade, 8-bit) | KAD2708L (-35 grade, 8-bit) |
| Pin-to-Pin Compatible | Reference | Yes - drop-in | Yes - drop-in | Yes - drop-in (LVDS variant) | Yes - drop-in (8-bit, LVDS) | Yes - drop-in (8-bit, LVDS, faster) |
| Param Match Percentage | 100% | 80% | 90% | 90% | 70% | 70% |
Key Differentiators
- Industry's lowest power 10-bit 275 MSPS pipelined ADC family (vs KAD2710C-21Q68 (210 MSPS sibling))
- Drop-in speed-grade scalability within one PCB layout (vs KAD2710C-10Q68 (105 MSPS sibling))
- LVCMOS output option avoids external termination resistors (vs KAD2710L-17Q68 (LVDS variant))
Design Notes
The 68-QFN exposed pad (e-pad) is the primary thermal path and must be soldered to a continuous ground plane with at least 8 thermal vias on a 0.3 mm pitch. Recommended via pattern: array of 0.3 mm via diameter on 0.5 mm grid, filled with solder or thermal epoxy. Without proper e-pad soldering, theta_JA rises from ~24 C/W to over 60 C/W, causing the converter to exceed 125C junction temperature at room ambient.
Separate the analog (1.8 V AVDD) and digital (3.3 V DVDD) ground domains with a single-point connection under the ADC. Route analog input traces as 50 ohm controlled-impedance microstrip with reference plane one layer below. Keep digital output traces short (under 50 mm) and 50 ohm terminated at the FPGA receiver; place 33 ohm series resistors within 5 mm of the ADC outputs to damp reflection ringing. Cross under the AIN/CLK traces at 90 degrees only, never parallel.
Do not DC-couple the analog input directly; AC-couple through a 0.1 uF ceramic capacitor to set the common-mode bias internally. Exceeding 2 Vpp input amplitude saturates the input T/H and triggers the OTR (over-range) flag - if it persists, attenuation is needed at the front-end. The CLKDIV input is not optional for low-jitter operation; if the divide-by-2 path is selected, ensure the input clock frequency is below the device's absolute maximum of 700 MHz to avoid latch-up.
Use a low-jitter clock source with sub-200 fs RMS jitter for input frequencies above 100 MHz to preserve SNR. A poor clock is the most common SNR degradation cause in pipelined ADC designs. For LVCMOS clocking, route the clock through a 33 ohm series resistor and place a 10 nF AC-coupling cap adjacent to CLK+; for LV-PECL clocks, use 100 ohm differential termination at the ADC clock pins. The DCLK output should fan out to no more than 4 FPGA clock inputs to limit loading.
Compliance Information
RoHS-compliant per Renesas product page (Q68 suffix indicates lead-free QFN package). Halogen-free per JEDEC JS709 / Renesas product characterization. AEC-Q100 not applicable - this is an industrial-grade converter, not automotive-qualified.
