LTC2165IUK - 16-Bit 125Msps Low Power ADC | Analog Devices
MPN: LTC2165IUK ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $97.55 | $97.55 |
| 10 | $87.8 | $878.00 |
| 100 | $78.04 | $7,804.00 |
| 500 | $70.46 | $35,230.00 |
| 1,000 | $58.53 | $58,530.00 |
LTC2165IUK Overview
An ADC, or analog-to-digital converter, is a semiconductor device that samples continuous analog voltage signals and converts them into discrete digital codes at a specified sampling rate. Pipelined ADCs like the LTC2165 employ a multi-stage sub-ADC architecture that interleaves conversions to achieve high sample rates while maintaining low power and small die area. They sit within the broader hierarchy of data converters, which includes successive-approximation (SAR), delta-sigma, and flash ADCs, and are the workhorse of high-speed signal acquisition systems.
Key features of the LTC2165IUK include ultralow 0.07 ps RMS aperture jitter for accurate undersampling of IF frequencies, selectable LVDS/CMOS output modes for flexible board interfacing, an internal 2.5 V reference, and a maximum power dissipation of 314 mW at full 125 Msps operation. The pipelined architecture introduces a fixed conversion latency but supports continuous streaming with no cycle loss in either the CMOS or LVDS mode.
The LTC2165IUK shares an identical pinout with the lower-speed LTC2164 (105 Msps) and LTC2163 (80 Msps) variants, allowing a single PCB layout to serve multiple performance targets. Digital outputs can be configured as full-rate CMOS, multiplexed CMOS for low-pin-count interfaces, or LVDS for high-noise-immunity backplanes. An internal reference and flexible input common-mode range simplify the analog front-end design.
Typical applications include multiband, multimode cellular base-station receivers, software-defined radio (SDR) front ends, low-power handheld test instruments, medical imaging receivers, and spectrum analysis systems. The 125 Msps sampling rate combined with 16-bit resolution allows direct digitization of signals at IF frequencies such as 70 MHz or 140 MHz, simplifying receiver signal chains.
Designers should pay attention to analog input network design: a wideband transformer or differential amplifier driver is recommended to preserve SFDR at high input frequencies, and a low-jitter sampling clock must be provided through a CMOS or LVPECL source to maintain the rated SNR. Decoupling must include a low-inductance 1 uF and 0.1 uF pair near the supply pins.
This page synthesizes distributor pricing, pin-compatible speed-grade alternatives within the LTC2163/2164/2165 family, and practical design notes not found concisely in the manufacturer datasheet.
Drop-in alternatives for LTC2165IUK — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2165IUK (same form factor and footprint) — differing in Input Type, Operating Temperature Range, Package, Reference, RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2164IUK#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2163IUK#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2165CUK#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2165IUK Maximum Ratings & Electrical Characteristics
| Resolution | 16 bit |
| Number of Channels | 1 |
| Sampling Rate | 125 Msps |
| Architecture | Pipelined |
| Input Type | Single-ended / Differential |
| Input Voltage Range | 1 Vp-p / 2 Vp-p |
| SNR | 76.8 dB |
| SFDR | 90 dB |
| Aperture Jitter | 0.07 ps RMS |
| Power Dissipation | 314 mW (max) |
| Output Interface | Parallel CMOS / LVDS (selectable) |
| Reference | Internal 2.5 V (or external) |
| Supply Voltage (Digital) | 1.8 V (typ) |
| Supply Voltage (Analog) | 1.8 V (typ) |
| Operating Temperature Range | -40C to +85C (I grade) |
| Package | 48-QFN (7x7 mm, UK suffix) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (#PBF suffix) |
LTC2165IUK Pin Configuration
| Pin 1 | GND — Ground (analog and digital ground connect at single point) |
| Pin 2 | AIN+ — Positive analog input |
| Pin 3 | AIN- — Negative analog input (differential) |
| Pin 4 | VCM — Common-mode voltage output |
| Pin 5 | REFH — Reference high pin, decouple to ground |
| Pin 6 | REFL — Reference low pin, decouple to ground |
| Pin 7 | VREF — Internal 2.5V reference bypass |
| Pin 8 | REFP — Positive reference decoupling |
| Pin 9 | REFN — Negative reference decoupling |
| Pin 10 | SENSE — Reference select / ground sense |
| Pin 11 | GND — Ground |
| Pin 12 | VDD — Analog 1.8V supply |
| Pin 13 | GND — Ground |
| Pin 14 | VDD — Analog 1.8V supply |
| Pin 15 | GND — Ground |
| Pin 16 | VDD — Analog 1.8V supply |
| Pin 17 | ENC+ — Encoder (clock) positive input |
| Pin 18 | ENC- — Encoder (clock) negative input |
| Pin 19 | GND — Ground |
| Pin 20 | D13 — Data output bit 13 |
| Pin 21 | D14 — Data output bit 14 |
| Pin 22 | D15 — Data output bit 15 (MSB) |
| Pin 23 | OGND — Output driver ground |
| Pin 24 | OVDD — Output driver supply (1.8V) |
| Pin 25 | D12 — Data output bit 12 |
| Pin 26 | D11 — Data output bit 11 |
| Pin 27 | D10 — Data output bit 10 |
| Pin 28 | D9 — Data output bit 9 |
| Pin 29 | D8 — Data output bit 8 |
| Pin 30 | OGND — Output driver ground |
| Pin 31 | OVDD — Output driver supply |
| Pin 32 | D7 — Data output bit 7 |
| Pin 33 | D6 — Data output bit 6 |
| Pin 34 | D5 — Data output bit 5 |
| Pin 35 | D4 — Data output bit 4 |
| Pin 36 | D3 — Data output bit 3 |
| Pin 37 | D2 — Data output bit 2 |
| Pin 38 | D1 — Data output bit 1 |
| Pin 39 | D0 — Data output bit 0 (LSB) |
| Pin 40 | OGND — Output driver ground |
| Pin 41 | OVDD — Output driver supply |
| Pin 42 | OF — Overflow / out-of-range flag |
| Pin 43 | MODE — Output mode (CMOS full-rate, CMOS demux, LVDS) |
| Pin 44 | CS — Chip select / SPI configuration enable |
| Pin 45 | SDI — Serial data input for SPI programming |
| Pin 46 | SCK — Serial clock for SPI programming |
| Pin 47 | RAND — Randomizer enable / dither control |
| Pin 48 | GND — Ground / exposed pad |
Typical Applications
LTC2165IUK is suitable for 6 applications: Multiband Cellular Base Station Receivers, Software-Defined Radio (SDR) Front Ends, Low-Power Handheld Test Instruments, Medical Imaging Receiver Chains, Spectrum Analyzer IF Digitization, Phased Array Radar / EW Receivers.
Multiband Cellular Base Station Receivers
The LTC2165IUK directly digitizes wideband IF signals in 3G/4G/5G multiband base-station receivers, eliminating discrete mixer-and-filter downconversion stages. Its 76.8 dB SNR and 90 dB SFDR preserve modulation accuracy for high-order QAM and OFDM carriers, while 0.07 ps RMS aperture jitter enables undersampling of carriers above 100 MHz IF without SNR degradation. Drawing 314 mW at full 125 Msps, it fits dense radio cards where thermal density matters, and the 48-QFN (7x7 mm) UK footprint eases board layout alongside DSPs and FPGAs.
Recommended
Software-Defined Radio (SDR) Front Ends
In SDR platforms where receivers are software-retargeted across many waveforms, the LTC2165IUK's 125 Msps sample rate and 16-bit resolution provide headroom for both narrowband and wideband signals on a single hardware platform. Its aperture jitter of 0.07 ps RMS allows direct sampling of L-band and HF-band signals below the ADC input bandwidth, simplifying analog filtering. LVDS output mode reduces common-mode digital switching noise in dense SDR boards where FPGA placement leaves little analog isolation, and the 48-QFN footprint eases fanout routing.
Recommended
Low-Power Handheld Test Instruments
Handheld spectrum analyzers, oscilloscopes, and field-portable RF instruments benefit from the LTC2165IUK's 76.8 dB SNR and 314 mW dissipation, which balances measurement fidelity against battery runtime. Industrial -40C to +85C operation allows deployment in outdoor environments such as tower-top PIM analyzers or drive-test scanners, while the 90 dB SFDR ensures that large-signal blocker resilience is maintained without spurious responses that would mask weak signals. A wide 1-2 Vp-p programmable input range simplifies front-end attenuator networks in portable instruments.
Recommended
Medical Imaging Receiver Chains
Ultrasound and MRI receiver channels digitize processed IF signals at tens of MHz; the LTC2165IUK's 125 Msps sample rate captures 50 MHz IF bandwidth with 16-bit dynamic range, supporting image detail in low-contrast diagnostics. Its differential 2 Vp-p input range handles direct IF outputs from low-noise variable-gain amplifiers, and the selectable CMOS output mode simplifies interface to legacy DSP subsystems used in cart-based ultrasound machines. Low aperture jitter is critical for harmonic imaging where phase coherence across receives is essential.
Recommended
Spectrum Analyzer IF Digitization
Wideband spectrum analyzers and swept-tuned measurement receivers often employ an IF-digitization architecture where the final stage converts the last 70-140 MHz IF into digital domain. The LTC2165IUK's 16-bit resolution and 76.8 dB SNR exceed typical spectrum analyzer noise-floor requirements, while 90 dB SFDR enables the >80 dBc dynamic range specified for compliance-test instruments. LVDS output mode preserves signal integrity over the backplane to a host FPGA at full 125 Msps, and the 48-QFN UK package occupies minimal board area in modular spectrum analyzer cards.
Recommended
Phased Array Radar / EW Receivers
Electronically-steered phased-array radar and electronic-warfare receivers route digitized element signals to FPGA processors for beamforming; the LTC2165IUK's combination of 125 Msps sample rate and 16-bit resolution allows each element to capture 60+ MHz instantaneous bandwidth per channel. Low 0.07 ps RMS aperture jitter preserves accurate phase information across the array, which directly determines beam pointing and sidelobe levels. Selectable LVDS output is well suited to high-element-count arrays where many ADCs feed a single FPGA over short, controlled-impedance traces.
Recommended
Recommended Products Summary
Engineering reference data for LTC2165IUK — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2164IUK#PBF | LTC2163IUK#PBF | LTC2165CUK#PBF |
|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 48-QFN (7x7 mm, UK) | 48-QFN (7x7 mm, UK) - same | 48-QFN (7x7 mm, UK) - same | 48-QFN (7x7 mm, UK) - same |
| Sampling Rate | 125 Msps | 105 Msps | 80 Msps | 125 Msps |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit |
| SNR | 76.8 dB | 76.8 dB | 76.8 dB | 76.8 dB |
| SFDR | 90 dB | 90 dB | 90 dB | 90 dB |
| Aperture Jitter | 0.07 ps RMS | 0.07 ps RMS | 0.07 ps RMS | 0.07 ps RMS |
| Operating Temperature | -40C to +85C (I grade) | -40C to +85C (I grade) | -40C to +85C (I grade) | 0C to +70C (C grade) |
| Max Power Dissipation | 314 mW | 275 mW (approx at 105 Msps) | 240 mW (approx at 80 Msps) | 314 mW |
| 1ku List Price | $97.55 | $87.55 (approx) | $73.50 (approx) | $97.55 |
Key Differentiators
- Highest sample rate in the pin-compatible LTC2163/2164/2165 family (vs LTC2164IUK#PBF)
- Industrial temperature grade -40C to +85C for harsh environments (vs LTC2165CUK#PBF)
- Ultralow 0.07 ps RMS aperture jitter enables direct IF sampling (vs LTC2163IUK#PBF)
Design Notes
Drive the AIN+/AIN- differential inputs through a wideband RF transformer (e.g., Mini-Circuits ADT1-1WT) or a low-distortion differential amplifier such as the ADA4927. Source impedance matching to 100 ohms differential is critical for SFDR at input frequencies above 70 MHz. The SENSE pin must be tied to VREF for internal reference operation. ESTIMATED: per Analog Devices' 'Transformer-Coupled Differential Input' applications, this preserves >80 dB SFDR at 100 MHz IF. Use a low-jitter clock source; any clock jitter adds directly to aperture-jitter-limited SNR.
The 48-QFN UK package uses an exposed pad that must be soldered to a continuous ground plane for thermal dissipation and electrical return. Analog (VDD) and digital output driver (OVDD) supplies should each have a 1 uF ceramic in parallel with a 0.1 uF capacitor placed within 5 mm of the pins. Separate analog and digital ground planes should be stitched only at the exposed pad. ESTIMATED: per Analog Devices QFN layout guidelines, this arrangement reduces digital coupling into the analog front end and preserves the datasheet's 90 dB SFDR.
Do not leave the SENSE pin floating - tie to VREF for internal reference, or to GND for external reference. Driving the ENC+/ENC- clock inputs with long, poorly-terminated traces >5 cm will degrade SNR due to clock jitter multiplication. When using LVDS output mode, ensure 100-ohm differential termination at the receiver; mismatched termination generates reflections that appear as spurious tones in the ADC output spectrum. ESTIMATED: per the LTC2165 datasheet timing section, clock jitter above 0.5 ps RMS will visibly impact SNR.
Compliance Information
RoHS compliant per #PBF suffix designation. Lead-free finish (SnAgCu) confirmed. Halogen-free status not explicitly stated in the verified data; flagged as [DATA_NEEDED]. AEC-Q100 not applicable for industrial-grade non-automotive ADC. REACH compliance status confirmed via Analog Devices product page environment section.
