LTC2188CUP - 16-Bit 20Msps Dual ADC | Analog Devices
MPN: LTC2188CUP ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $64.5 | $64.50 |
| 10 | $58.05 | $580.50 |
| 100 | $51.6 | $5,160.00 |
| 500 | $46.44 | $23,220.00 |
| 1,000 | $41.86 | $41,860.00 |
LTC2188CUP Overview
An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog signals into discrete digital codes at a sample rate determined by an external clock. Pipelined ADCs like the LTC2188CUP use multiple low-resolution stages to digitize one input sample per clock cycle after an initial pipeline latency, achieving a balance of high sample rate, moderate resolution, and low power consumption. They sit within the broader hierarchy of signal chain components: ADC -> data converter -> mixed-signal IC -> semiconductor, and are typically paired with low-noise front-end amplifiers, anti-alias filters, and FPGA or ASIC capture logic.
Key features of the LTC2188CUP include dual simultaneous 20 Msps channels, 16-bit resolution, 77 dB SNR at 10 MHz input, 90 dB SFDR, support for CMOS and DDR LVDS output interfaces, an internal sample-and-hold, and programmable analog input span. Integrated digital features such as data-ready outputs and pattern generation simplify board bring-up and FPGA/ASIC handshake design. The part is offered in commercial (C) and industrial/extended temperature grades.
The LTC2188CUP uses a multi-stage pipelined core with proprietary dithering techniques that linearize the transfer function and improve small-signal SFDR. A differential input architecture rejects common-mode noise and even-order harmonics, while on-chip bias generation reduces the external component count. The device consumes roughly 65 mW per channel at 20 Msps and includes power-down modes for portable or multi-channel systems where thermal budget is constrained.
Typical applications include digital oscilloscopes and wideband data acquisition, communications receivers and software-defined radio (SDR) front-ends, medical ultrasound beamformers, and industrial imaging systems. The dual-channel simultaneous sampling makes the LTC2188CUP particularly well-suited to I/Q baseband digitizers and multi-antenna diversity receivers where channel-to-channel timing alignment is critical.
When designing with the LTC2188CUP, pay close attention to the analog input network: a wideband, differential, low-distortion front-end (such as the ADA4932 or LTC6406) is typically required to preserve the converter's 90 dB SFDR. Decouple the AVDD and DVDD rails with separate low-ESR ceramic capacitors placed as close as possible to the package pins, and route differential pairs with controlled 100-ohm impedance on the PCB.
This page synthesizes verified distributor pricing, drop-in alternatives drawn from the LTC2188 family (LTC2185, LTC2186, LTC2187) plus pin-compatible ADI 16-bit ADCs, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for LTC2188CUP — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2188CUP (same form factor and footprint) — differing in Number of Channels, Package, Resolution, SNR, Sample Rate.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2187CUP
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2186CUP
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2185CUP
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2188CUP#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2188CUP#TRPBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2188IUP
✅ Drop-In✓ In Stock
$49.2 / Unit
View Datasheet →LTC2188CUP Maximum Ratings & Electrical Characteristics
| Manufacturer | Analog Devices (Linear Technology) |
| MPN | LTC2188CUP |
| Function | Dual-channel simultaneous-sampling 16-bit ADC |
| Resolution | 16 bits |
| Number of Channels | 2 channels (simultaneous sampling) |
| Sample Rate | 20 Msps per channel |
| Architecture | Pipelined |
| Input Type | Differential |
| SNR | 77 dB at 10 MHz input |
| SFDR | 90 dB |
| Data Output Interface | CMOS / DDR LVDS (selectable) |
| Input Range | Programmable, 1 Vp-p to 2 Vp-p differential |
| Analog Supply Voltage | 1.8 V |
| Digital Supply Voltage | 1.8 V / 2.5 V / 3.3 V (depends on I/O mode) |
| Power Consumption | 125 mW total (typical, both channels at 20 Msps) |
| Operating Temperature Range (C grade) | 0 C to +70 C |
| Package | 64-pin QFN (UP), 9x9 mm |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (PBF suffix) |
| MSL Level | 1 (per JEDEC J-STD-020) |
LTC2188CUP 64-pin qfn (up), 9x9 mm Pin Configuration Guide
Pin configuration for LTC2188CUP (64-pin qfn (up), 9x9 mm package). This analog component features input, output, and power supply pins. Refer to the manufacturer datasheet for offset null, compensation, and enable pin configurations. Ideal for signal conditioning and amplifier circuits.
No detailed pinout data available for LTC2188CUP.
Refer to the datasheet for full pin configuration.
Typical Applications
LTC2188CUP is suitable for 6 applications: Wideband Digital Oscilloscopes, Software-Defined Radio (SDR) Baseband, Medical Ultrasound Beamformers, Industrial Imaging and Inspection, Multi-Antenna Diversity Receivers, Portable and Battery-Powered Data Acquisition.
Wideband Digital Oscilloscopes
The LTC2188CUP's 16-bit resolution and 20 Msps simultaneous sampling on two channels make it ideal for two-channel bench and modular oscilloscopes targeting 1 MHz to 10 MHz bandwidth. Its 77 dB SNR and 90 dB SFDR enable clean capture of small signals riding on large DC offsets, while the dual simultaneous inputs preserve inter-channel phase - critical for power-electronics probing and differential measurements. Designers pair the converter with an ADI ADA4932 differential ADC driver to preserve SFDR across the full analog front-end. The 64-pin QFN (UP) 9x9 mm footprint fits inside compact handheld oscilloscope form factors where thermal dissipation is constrained.
Recommended
Software-Defined Radio (SDR) Baseband
In communications receivers, the LTC2188CUP simultaneously digitizes the I and Q baseband outputs from a quadrature demodulator, preserving 90-degree phase relationships essential for EVM. The 77 dB SNR supports high-order modulation schemes (64-QAM, 256-QAM), while the 90 dB SFDR ensures spurs fall well below the noise floor of cellular and Wi-Fi standards. CMOS output mode reduces FPGA I/O bank cost; DDR LVDS mode minimizes switching noise that would otherwise degrade SNR. Anti-alias filters ahead of the analog inputs typically roll off above 10 MHz to take full advantage of the 20 Msps Nyquist bandwidth.
Recommended
Medical Ultrasound Beamformers
Portable and cart-based ultrasound systems rely on multi-channel simultaneous sampling to capture echo data from 16 to 256 transducer elements. The LTC2188CUP's dual-channel architecture allows two beamformer channels to be digitized with matched latency, supporting phased-array imaging where channel-to-channel skew must stay below 100 ps. The 1.8 V analog supply and 125 mW total power dissipation help manage thermal budgets in handheld probes. The 16-bit dynamic range captures both strong specular reflections and weak tissue harmonics without range-gating, while CMOS output mode simplifies routing to FPGA-based beamforming pipelines. Designers typically add an ADI AD9271 front-end for integrated LNA/VGA/AAF ahead of the converter.
Recommended
Industrial Imaging and Inspection
Multi-spectral line-scan cameras, vibration sensors, and non-destructive testing instruments all benefit from the LTC2188CUP's dual-channel simultaneous sampling. The 20 Msps rate per channel supports line-scan rates up to 20 kHz per channel when operating in 2:1 mux mode, while the 16-bit depth captures subtle intensity variations needed for defect detection. The 0 C to +70 C commercial temperature range (extended to -40 to +85 C with the IUP variant) covers most factory environments without additional thermal management. The QFN-64 9x9 mm package fits inside sealed camera heads and provides good thermal coupling to the chassis for heat dissipation.
Recommended
Multi-Antenna Diversity Receivers
MIMO and antenna-diversity receivers sample two or more antenna paths concurrently, requiring matched channel latency across a wide bandwidth. The LTC2188CUP's simultaneous dual sampling eliminates inter-channel skew caused by sequential converters, simplifying baseband combiner design and improving receiver sensitivity in fading channels. The 77 dB SNR preserves high-order modulation bit-error rates, while CMOS or DDR LVDS outputs feed directly into FPGA digital signal-processing pipelines. Designers typically sample the I/Q outputs of two radio receivers, using one converter channel per receiver for optimal phase alignment in beam-forming or diversity-combining algorithms.
Recommended
Portable and Battery-Powered Data Acquisition
Field data loggers, handheld spectrum analyzers, and portable vibration monitors benefit from the LTC2188CUP's 125 mW total power dissipation - the lowest in the LTC2188 family for battery-life design. Power-down modes (per ADI datasheet) drop consumption further between capture bursts, extending runtime on a single charge. The dual channels capture both a measurement signal and a reference temperature sensor simultaneously, eliminating drift error in low-frequency environmental tests. The QFN-64 9x9 mm package keeps board area under 1 cm^2, leaving room for analog front-end and isolated USB or Bluetooth interfaces in handheld enclosures.
Recommended
Recommended Products Summary
Engineering reference data for LTC2188CUP — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2187CUP | LTC2186CUP | LTC2185CUP | LTC2188IUP |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | QFN-64 (UP) 9x9 mm | QFN-64 (UP) 9x9 mm - same | QFN-64 (UP) 9x9 mm - same | QFN-64 (UP) 9x9 mm - same | QFN-64 (UP) 9x9 mm - same |
| Resolution | 16 bits | 16 bits | 16 bits | 16 bits | 16 bits |
| Sample Rate | 20 Msps | 10 Msps (-50%) | 5 Msps (-75%) | 1 Msps (-95%) | 20 Msps (same) |
| Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) |
| SNR | 77 dB at 10 MHz | 77 dB | 77 dB | 77 dB | 77 dB |
| SFDR | 90 dB | 90 dB | 90 dB | 90 dB | 90 dB |
| Temperature Range | 0 C to +70 C (C grade) | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C | -40 C to +85 C (industrial) |
Key Differentiators
- Highest sample rate within the LTC2188 16-bit dual family (vs LTC2187CUP)
- Dual simultaneous sampling preserves inter-channel phase (vs LTC2208 (single-channel ADC family))
- Lowest power in the family at given sample rate (vs LTC2186CUP at the same footprint)
- Industrial-grade drop-in option exists for wider temperature range (vs LTC2188IUP)
Design Notes
Route the analog differential inputs (AIN+/AIN-) as a 100-ohm differential pair with controlled impedance, keeping length matching within 0.5 mm to preserve SFDR at 90 dB. Place the input coupling network (transformer or driver + balun) within 5 mm of the converter pins and keep digital CMOS/LVDS output traces physically separated from analog inputs. The exposed pad (EP) of the QFN-64 package must be soldered to a continuous ground plane stitched with at least nine thermal vias to dissipate ~125 mW without exceeding 70 C junction rise.
Decouple the AVDD and DVDD rails independently: a 10 uF bulk + 0.1 uF + 1 nF capacitor stack adjacent to the package, with the smallest cap closest to the pin. Use a ferrite bead between the analog and digital supplies to break ground loops. The 1.8 V analog LDO must have < 10 uVrms noise (recommended parts: ADP151, LT3042) - any supply noise above 10 kHz directly couples to the SNR and degrades the 77 dB spec. Power-down pin (PD) can reduce quiescent current to ~1 mA between capture bursts in portable applications.
Clock jitter is the dominant error source for an IF-sampling ADC at 10 MHz+ input. Apply a low-jitter clock (AD9516-0BCPZ or equivalent) with sub-200-fs RMS jitter to the CLK+ / CLK- differential inputs to preserve the 90 dB SFDR. Use a high-bandwidth transformer (e.g., ADT1-1WT) or a differential clock buffer to translate a single-ended CMOS reference clock to the required differential format. Long clock traces radiate energy into adjacent pairs; route the clock on an inner layer with continuous ground references on both sides.
At continuous 20 Msps dual-channel operation, total dissipation is ~125 mW (typical), keeping the QFN-64 junction-to-ambient rise around 25-30 C/W above ambient with proper PCB layout. In sealed enclosures without airflow, derate ambient to 50 C maximum and verify with a thermocouple on the EP. For outdoor or industrial applications (-40 to +85 C), select the LTC2188IUP industrial grade instead of the LTC2188CUP commercial grade - same drop-in pinout, same 90 dB SFDR, but the IUP variant is qualified across the wider temperature range.
Compliance Information
PBF suffix confirms lead-free / RoHS compliance per ADI product family suffix convention. This C-grade part is not AEC-Q100 qualified (use automotive-grade ADI ADCs from the AD7278 / ADI automotive family for that requirement).
