LTC2220IUP-1 - 12-Bit 185Msps ADC, 64-QFN | Analog Devices
MPN: LTC2220IUP-1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $42.5 | $42.50 |
| 10 | $38.25 | $382.50 |
| 100 | $33.9 | $3,390.00 |
| 500 | $30.1 | $15,050.00 |
| 1,000 | $26.75 | $26,750.00 |
LTC2220IUP-1 Overview
An ADC (analog-to-digital converter) is a semiconductor device that converts continuous-time analog signals into discrete digital codes, enabling downstream processing by DSPs, FPGAs, or microcontrollers. Within the broader signal chain hierarchy, the ADC sits between the analog front end (amplifiers, filters) and the digital processing block. Pipelined ADCs in particular use a multi-stage architecture that delivers high sample rates (tens to hundreds of Msps) with moderate resolution (10-14 bits), making them the workhorse for wireless baseband, radar, test instrumentation, and software-defined radio.
Key features of the LTC2220IUP-1 include differential or single-ended input flexibility, parallel CMOS/CMOS-compatible output, integrated bandgap reference, and an optional output dither mode for improved SFDR at small input levels. The pipelined architecture provides inherent sample-and-hold operation, eliminating the need for an external SHA. The 64-QFN exposed-pad package provides a low thermal-resistance path, allowing the device to operate at the industrial -40C to +85C range without additional heatsinking at typical power levels.
Typical applications include cellular base-station receiver IF digitization, cable-modem downstream capture, high-end medical imaging front ends, test and measurement digitizers, and radar/sonar signal processing. The 775 MHz analog input bandwidth also enables direct IF sampling of signals in the 70-200 MHz range, simplifying the receiver chain by eliminating a down-conversion stage.
When designing with this part, allocate adequate PCB area for the exposed pad and stitch its thermal vias to an internal ground plane. The analog input pins should be DC-biased through a common-mode network; bypassing must use low-ESR ceramic capacitors placed within 5 mm of the supply pins. Output data timing is referenced to an external clock, and trace-length matching on the output bus is critical to maintain setup/hold margins above 100 Msps.
This page synthesizes distributor pricing, pin-compatible drop-in alternatives from the LTC2220 family, and practical PCB layout notes not collected in the manufacturer datasheet alone. All specifications are extracted from the Linear Technology/Analog Devices LTC2220 datasheet and DigiKey listing as of 2026-10-13.
Drop-in alternatives for LTC2220IUP-1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2220IUP-1 (same form factor and footprint) — differing in Input Type, Operating Temperature, Package, Resolution, RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2220IUP
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2220CUP-1
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2220IUP#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2221IUP
✅ Drop-In✓ In Stock
$55.26 / Unit
View Datasheet →LTC2208IUP-14
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2220IUP-1 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bits |
| Architecture | Pipelined |
| Number of Input Channels | 1 |
| Input Type | Differential or single-ended |
| SNR | 67.5 dB at 140 MHz input |
| SFDR | 80 dB at 170 MHz input |
| Full-Power Input Bandwidth | 775 MHz |
| Supply Voltage | 3.3 V (single) |
| Power Dissipation | 890 mW at 170 Msps / 660 mW at 135 Msps |
| Output Interface | Parallel CMOS |
| Package | 64-pin QFN (9x9 mm) with exposed pad |
| Operating Temperature | -40 C to +85 C (Industrial) |
| Mounting Type | Surface Mount |
| Temperature Grade | Industrial |
| Screening Level | Industrial |
| RoHS Status | Compliant |
LTC2220IUP-1 Pin Configuration
| Pin 1 | GND — Ground |
| Pin 2 | VREF — Reference voltage decoupling |
| Pin 3 | AIN+ — Differential analog input positive |
| Pin 4 | AIN- — Differential analog input negative |
| Pin 5 | VCM — Common-mode voltage output |
| Pin 6 | SENSE — Reference configuration |
| Pin 7 | GND — Ground |
| Pin 8 | VDD — 3.3 V analog supply |
| Pin 9 | OGND — Output driver ground |
| Pin 10 | OVDD — Output driver supply |
| Pin 11 | D11 — Data output bit 11 (MSB) |
| Pin 12 | D10 — Data output bit 10 |
| Pin 13 | D9 — Data output bit 9 |
| Pin 14 | D8 — Data output bit 8 |
| Pin 15 | D7 — Data output bit 7 |
| Pin 16 | D6 — Data output bit 6 |
| Pin 17 | D5 — Data output bit 5 |
| Pin 18 | D4 — Data output bit 4 |
| Pin 19 | D3 — Data output bit 3 |
| Pin 20 | D2 — Data output bit 2 |
| Pin 21 | D1 — Data output bit 1 |
| Pin 22 | D0 — Data output bit 0 (LSB) |
| Pin 23 | OGND — Output driver ground |
| Pin 24 | OVDD — Output driver supply |
| Pin 25 | CLKOUT — Clock output (for data capture) |
| Pin 26 | CLKOUT- — Differential clock output negative |
| Pin 27 | OGND — Output driver ground |
| Pin 28 | OVDD — Output driver supply |
| Pin 29 | DITH — Dither enable |
| Pin 30 | SHDN — Shutdown (active high) |
| Pin 31 | MODE — Output mode select |
| Pin 32 | OE — Output enable |
| Pin 33 | GND — Ground |
| Pin 34 | VDD — 3.3 V analog supply |
| Pin 35 | GND — Ground |
| Pin 36 | CLK+ — Differential clock input positive |
| Pin 37 | CLK- — Differential clock input negative |
| Pin 38 | GND — Ground |
| Pin 39 | VDD — 3.3 V analog supply |
| Pin 40 | GND — Ground |
| Pin 41 | VDD — 3.3 V analog supply |
| Pin 42 | GND — Ground |
| Pin 43 | VDD — 3.3 V analog supply |
| Pin 44 | GND — Ground |
| Pin 45 | VDD — 3.3 V analog supply |
| Pin 46 | GND — Ground |
| Pin 47 | VDD — 3.3 V analog supply |
| Pin 48 | GND — Ground |
| Pin 49 | VDD — 3.3 V analog supply |
| Pin 50 | GND — Ground |
| Pin 51 | VDD — 3.3 V analog supply |
| Pin 52 | GND — Ground |
| Pin 53 | VDD — 3.3 V analog supply |
| Pin 54 | GND — Ground |
| Pin 55 | VDD — 3.3 V analog supply |
| Pin 56 | GND — Ground |
| Pin 57 | VDD — 3.3 V analog supply |
| Pin 58 | GND — Ground |
| Pin 59 | VDD — 3.3 V analog supply |
| Pin 60 | GND — Ground |
| Pin 61 | NC — Not connected (per datasheet) |
| Pin 62 | NC — Not connected (per datasheet) |
| Pin 63 | NC — Not connected (per datasheet) |
| Pin 64 | NC — Not connected (per datasheet) |
| Pin 65 | EP — Exposed pad - thermal/ground, must be soldered to PCB ground plane |
Typical Applications
LTC2220IUP-1 is suitable for 6 applications: Cellular Base-Station Receiver IF Digitization, Cable Modem Downstream QAM Capture, Test and Measurement Digitizer, Radar and Sonar Signal Processing, Medical Imaging Front End, Software-Defined Radio Receiver.
Cellular Base-Station Receiver IF Digitization
The LTC2220IUP-1 is well matched to digitize the IF stage of a cellular base-station receiver, where the 775 MHz full-power input bandwidth enables direct sampling of 70-200 MHz intermediate frequencies without an analog down-conversion stage. At 185 Msps, the converter oversamples a 30 MHz W-CDMA or LTE channel by more than 6x, pushing aliased quantization noise well above the signal band and easing the analog anti-alias filter. The 67.5 dB SNR and 80 dB SFDR deliver the dynamic range needed for multi-carrier GSM/UMTS capture, and the parallel CMOS output bus streams directly into an FPGA digital down-converter. Designers should place the LTC2220IUP-1 downstream of a differential IF amplifier such as the AD8138 and use a low-noise LT1763 LDO on the 3.3 V analog supply.
Recommended
Cable Modem Downstream QAM Capture
Cable-modem downstream paths carry 64-/256-QAM signals centered near 40-100 MHz that demand high SFDR to keep constellation EVM within DOCSIS limits. The LTC2220IUP-1's 80 dB SFDR at 170 MHz input and 67.5 dB SNR support symbol rates up to 7 MSps with margin for cable-plant impairments. The 185 Msps sample rate allows the ADC to capture multiple downstream carriers simultaneously, enabling a single-conversion tunerless architecture. The 64-QFN (9x9) package keeps the analog input traces short, which is critical at IF frequencies, and the single 3.3 V supply simplifies the cable-modem power tree. Pair the ADC with an FPGA-based QAM demodulator and a precision timing reference.
Recommended
Test and Measurement Digitizer
Portable and benchtop digitizers benefit from the LTC2220IUP-1's combination of 12-bit resolution, 185 Msps sample rate, and 775 MHz analog input bandwidth. This bandwidth allows the digitizer to capture repetitive and single-shot transients up to roughly 200 MHz without an analog front-end down-converter, reducing bill of materials and calibration complexity. The pipelined architecture provides inherent sample-and-hold operation, and the parallel CMOS output is easy to capture with an FPGA or ASIC. The industrial -40 C to +85 C range supports outdoor and industrial digitizer use cases. Estimated: at 185 Msps, the part dissipates approximately 970 mW - use a 4-layer FR-4 board with a stitched exposed-pad thermal pour.
Recommended
Radar and Sonar Signal Processing
Pulsed-radar and sonar front ends require wide analog input bandwidth to capture the IF return signal with high dynamic range. The LTC2220IUP-1's 775 MHz input bandwidth and 185 Msps sample rate can digitize IF frequencies up to ~200 MHz, supporting surface and airborne radar IF strips centered in the 70-160 MHz range. The 80 dB SFDR is critical for detecting small targets in the presence of large clutter, and the pipelined architecture handles the pulse-repetition-frequency gating required for range-Doppler processing. For phased-array systems, multiple LTC2220IUP-1 devices can be clocked from a common low-jitter source to maintain channel-to-channel coherence. Place the ADC close to the analog mixer and use controlled-impedance 50 ohm microstrip for the IF input.
Recommended
Medical Imaging Front End
Ultrasound and other medical imaging systems rely on high-dynamic-range ADCs to capture small echoes against large transmit leakage. The LTC2220IUP-1's 67.5 dB SNR and 80 dB SFDR provide the dynamic range needed to resolve sub-millimeter tissue features, while its 185 Msps sample rate supports up to ~90 MHz of usable analog input bandwidth per channel. The 64-QFN (9x9) package with exposed pad supports the thermal dissipation required for continuous operation in cart-based ultrasound systems. The differential analog input simplifies interface to a TGC (time-gain-control) amplifier chain. For portable ultrasound, the part can be duty-cycled with its low-power shutdown mode to extend battery life.
Recommended
Software-Defined Radio Receiver
Software-defined radio (SDR) platforms place the ADC as close to the antenna as possible, and the LTC2220IUP-1's 775 MHz input bandwidth enables direct sampling of HF, VHF, and lower-UHF bands without an analog mixer. At 185 Msps, the part provides enough oversampling to relax the analog anti-alias filter and improve dynamic range through digital filtering. The 12-bit resolution is sufficient for narrow-band amateur and commercial receivers, and the parallel CMOS output drops easily into an FPGA-based DDC. The industrial temperature grade supports outdoor and mobile deployments. Estimated: place a 1:1 balun (such as ADT1-1WT) at the analog input to convert single-ended antenna signals to the differential ADC input.
Recommended
Recommended Products Summary
Engineering reference data for LTC2220IUP-1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2220IUP | LTC2220CUP-1 | LTC2220IUP#PBF | LTC2221IUP | LTC2208IUP-14 |
|---|---|---|---|---|---|---|
| Package | 64-QFN (9x9) | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 14 bits |
| Sample Rate | 185 Msps | 170 Msps | 185 Msps | 170 Msps | 135 Msps | 130 Msps |
| Operating Temperature | -40 C to +85 C (Industrial) | -40 C to +85 C | 0 C to +70 C (Commercial) | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
Key Differentiators
- Highest sample rate in the LTC2220 family at 185 Msps (vs LTC2220IUP)
- Industrial -40 C to +85 C temperature range (vs LTC2220CUP-1)
- Drop-in compatible with full LTC2220/2208/2221/2240 family (vs LTC2208IUP-14)
Design Notes
The 64-QFN (9x9) package requires the exposed pad (pin 65) to be soldered to a ground pour with a stitched array of thermal vias (typically 5x5 vias at 0.3 mm pitch). Place 0.1 uF and 10 uF X7R ceramic bypass capacitors within 5 mm of each VDD/OVDD pin; keep the analog and digital supply traces separate and join them only at the ADC. The analog input traces should be routed as a 100 ohm differential pair with length matching within 0.5 mm to preserve SFDR. Estimated: at 185 Msps the part draws approximately 290 mA from the 3.3 V analog supply, so use a 2 oz copper pour to keep IR drop below 5 mV.
The LTC2220IUP-1 has 775 MHz of analog input bandwidth, which means any common-mode noise above ~100 MHz can couple directly into the input. Use an AD8138 or similar differential driver with at least 70 MHz of -3 dB bandwidth, and provide a clean common-mode bias through the VCM pin. Series ferrite beads on the analog supply lines (600 ohm at 100 MHz) isolate the ADC from digital switching noise. Source-terminate the 12-bit parallel CMOS output bus to match the FPGA trace impedance (typically 50 ohm) to avoid reflections that corrupt setup/hold timing at 185 Msps.
Do not float the SENSE pin - it must be tied to VDD or GND to configure internal reference scaling. Floating CLK+ or CLK- causes the internal bias network to drift and degrades SNR by 3-5 dB. When the SHDN pin is asserted, the output bus goes to high-impedance, but the analog input remains powered; deassert SHDN only after the clock is stable. Avoid driving the analog input beyond 2 V peak-to-peak differential - the integrated ESD diodes clamp at lower voltages and SFDR degrades rapidly above the linear input range. Estimated: at 185 Msps with a 70 MHz input, the part dissipates approximately 1.0 W, which the 4-layer board with EP vias can handle without an external heatsink.
The 64-QFN package with the exposed pad has a typical theta_JA of around 28 C/W on a 4-layer JEDEC test board. At maximum 185 Msps sample rate, the device draws approximately 290 mA from 3.3 V, so power dissipation is roughly 1.0 W. With 28 C/W theta_JA, this gives a 28 C junction-temperature rise above ambient, keeping Tj well within the 125 C maximum at 85 C ambient. For continuous operation in a sealed enclosure, add 1 square inch of copper area on the top layer to reduce theta_JA toward 20 C/W and improve long-term reliability.
Compliance Information
RoHS and REACH compliant per Analog Devices material declaration; lead-free matte-tin finish supports Pb-free reflow up to 260 C peak per JEDEC J-STD-020. Not AEC-Q100 qualified (consumer/comms grade). Halogen-free per industry-standard e4 termination finish.
