LTC2256IUJ-12 - 12-Bit 25 MSPS Ultra-Low Power ADC | Analog Devices
MPN: LTC2256IUJ-12 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.27 | $8.27 |
| 10 | $7.45 | $74.50 |
| 100 | $6.4 | $640.00 |
| 500 | $5.55 | $2,775.00 |
| 1,000 | $4.9 | $4,900.00 |
LTC2256IUJ-12 Overview
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous-time, continuous-amplitude analog signals into discrete-time, discrete-amplitude digital codes. The LTC2256IUJ-12 belongs to the pipelined ADC sub-family, which uses a multi-stage switched-capacitor architecture to achieve high sampling rates (tens of MSPS) while keeping per-stage power dissipation modest. Within the broader taxonomy, this device is a successive-approximation/pipelined hybrid low-power ADC, classified under data converters -> ADC -> high-speed pipelined ADC -> mixed-signal IC -> semiconductor. Pipelined ADCs are the workhorse of communication baseband, IF sampling, and imaging front-ends because they balance speed, resolution, and power efficiency better than flash or SAR alternatives in the 8- to 16-bit, 20-200 MSPS range.
Key features include ±0.3 LSB INL (typical), ±0.1 LSB DNL (typical), no missing codes over temperature, and 0.3 LSB RMS transition noise. The digital outputs are software-configurable: full-rate CMOS, double-data-rate (DDR) CMOS, or DDR LVDS, allowing the same part to interface with FPGAs, ASICs, or standard microprocessors. A separate output power supply pin (OVDD) lets the CMOS output swing range from 1.2 V to 1.8 V, simplifying level translation to 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V host logic without external level shifters.
Architecturally, the LTC2256IUJ-12 uses a multi-bit-per-stage pipelined front-end followed by digital error correction, which both reduces the number of required sample-and-hold amplifier stages and improves linearity. The integrated input buffer accepts differential or single-ended drive, and the integrated reference can be bypassed for an external reference in precision applications. The 40-QFN exposed-pad package provides a low thermal resistance path, enabling operation across the -40 °C to +85 °C industrial temperature range without forced-air cooling.
Typical applications include communications IF/baseband sampling, portable instrumentation, ultrasound and medical imaging front-ends, and low-power multi-channel data acquisition systems. Its 1.8 V analog supply and configurable output swings make it especially well suited to battery-powered or FPGA-co-designed platforms. When designing with this ADC, observe the datasheet-recommended input common-mode voltage, drive the clock with a low-jitter source, and provide a clean 1.8 V LDO upstream to preserve SNR. Decouple AVDD with 10 µF + 0.1 µF capacitors placed as close to the supply pins as possible, and tie the exposed pad to a solid ground plane for thermal dissipation. This page synthesizes distributor pricing, drop-in alternatives from the same ADI pin-compatible family, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for LTC2256IUJ-12 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2256IUJ-12 (same form factor and footprint) — differing in Input Type, RoHS Status, Analog Supply Voltage, Data Interface, Package.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2257IUJ-12
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2258IUJ-12
✅ Drop-In✓ In Stock
$28.2 / Unit
View Datasheet →LTC2256CUJ-12
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$17.2 / Unit
View Datasheet →LTC2256IUJ-14
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LTC2265CUJ-12
✅ Drop-In✓ In Stock
$22.4 / Unit
View Datasheet →LTC2256IUJ-12 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bit |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Sampling Rate | 25 MSPS |
| Input Type | Differential, Single-Ended |
| Data Interface | Serial, SPI |
| Analog Supply Voltage | 1.8 V (single supply) |
| Output Supply Voltage (OVDD) | 1.2 V to 1.8 V |
| Output Mode | Full-rate CMOS, DDR CMOS, or DDR LVDS |
| INL (typical) | ±0.3 LSB |
| DNL (typical) | ±0.1 LSB |
| Missing Codes | None over temperature |
| Transition Noise | 0.3 LSB RMS |
| Package | 40-Lead QFN (6 mm x 6 mm x 0.75 mm with EP) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
LTC2256IUJ-12 Pin Configuration
| Pin 1 | GND — Ground reference |
| Pin 2 | INA+ — Differential analog input (positive) |
| Pin 3 | INA- — Differential analog input (negative) |
| Pin 4 | GND — Ground reference |
| Pin 5 | REF — Reference voltage bypass node |
| Pin 6 | REFOUT — Internal reference output |
| Pin 7 | AVDD — 1.8 V analog supply |
| Pin 8 | GND — Ground reference |
| Pin 9 | AVDD — 1.8 V analog supply |
| Pin 10 | GND — Ground reference |
| Pin 11 | VCM — Common-mode voltage output |
| Pin 12 | AVDD — 1.8 V analog supply |
| Pin 13 | GND — Ground reference |
| Pin 14 | CLK+ — Differential clock input (positive) |
| Pin 15 | CLK- — Differential clock input (negative) |
| Pin 16 | GND — Ground reference |
| Pin 17 | OVDD — Output supply voltage (1.2 V to 1.8 V) |
| Pin 18 | OGND — Output ground |
| Pin 19 | D0/DDR — Digital output bit 0 / DDR data |
| Pin 20 | D1 — Digital output bit 1 |
| Pin 21 | D2 — Digital output bit 2 |
| Pin 22 | D3 — Digital output bit 3 |
| Pin 23 | D4 — Digital output bit 4 |
| Pin 24 | D5 — Digital output bit 5 |
| Pin 25 | D6 — Digital output bit 6 |
| Pin 26 | D7 — Digital output bit 7 |
| Pin 27 | D8 — Digital output bit 8 |
| Pin 28 | D9 — Digital output bit 9 |
| Pin 29 | D10 — Digital output bit 10 |
| Pin 30 | D11 — Digital output bit 11 (LSB) |
| Pin 31 | OGND — Output ground |
| Pin 32 | OVDD — Output supply voltage |
| Pin 33 | OGND — Output ground |
| Pin 34 | MODE — Output mode select (CMOS/DDR/LVDS) |
| Pin 35 | OF — Output format / data clock |
| Pin 36 | CS — Chip select / SPI enable |
| Pin 37 | SCLK — SPI serial clock |
| Pin 38 | SDI — SPI serial data input |
| Pin 39 | SDO — SPI serial data output |
| Pin 40 | GND — Ground reference |
Typical Applications
LTC2256IUJ-12 is suitable for 6 applications: Communications IF/Baseband Sampling, Portable Instrumentation Data Acquisition, Medical Ultrasound Imaging Front-End, Multi-Channel Data Acquisition Systems, Software-Defined Radio Receiver, Industrial Vibration Monitoring.
Communications IF/Baseband Sampling
The LTC2256IUJ-12's 25 MSPS sampling rate and 12-bit resolution make it well suited to communications IF and baseband signal chains. Its 0.3 LSB RMS transition noise preserves SNR in narrowband demodulation, and the configurable DDR LVDS output simplifies routing to an FPGA demodulator. Placed at the output of an IF mixer and SAW filter chain, it digitizes a 10-25 MHz IF with adequate headroom for digital downconversion. The 1.8 V single-rail analog supply reduces thermal budget in multi-channel receiver cards, and the small 40-QFN footprint enables dense channel layouts in MIMO and software-defined radio boards.
Recommended
Portable Instrumentation Data Acquisition
The LTC2256IUJ-12 is an excellent fit for handheld and battery-powered data acquisition systems where low power and small size matter. Its 1.8 V single analog supply and 12-bit resolution keep total board power well under 100 mW per channel, extending run-time in field instruments. The configurable CMOS or LVDS output interfaces directly to low-power FPGAs such as the Lattice ECP5 or Microchip IGLOO2, and the 6x6 mm QFN footprint leaves room for analog front-end signal conditioning on a small PCB. Use it in oscilloscope front-end digitizers, environmental loggers, and portable spectrum analyzer IF sections.
Recommended
Medical Ultrasound Imaging Front-End
The LTC2256IUJ-12 fits low-channel-count or portable ultrasound imaging front-ends well. Its 12-bit resolution captures time-gain-compensated envelope data with adequate dynamic range for diagnostic imaging, while the 25 MSPS rate supports conventional beamforming at typical probe center frequencies. Placed after the TGC amplifier and LNA chain, it digitizes the demodulated echo at 1.8 V single supply, dissipating less than 30 mW per channel to keep thermal load low. The 40-QFN package supports dense probe-head multiplexer designs, and the LVDS output mode routes data to a backend FPGA over short matched-length traces.
Recommended
Multi-Channel Data Acquisition Systems
The LTC2256IUJ-12's single-channel 1.8 V architecture is well suited to multi-channel data acquisition systems where one ADC per channel simplifies synchronization. The 12-bit resolution and 25 MSPS rate cover most industrial vibration, acoustic, and seismic monitoring applications. Placed after a per-channel anti-alias filter and instrumentation amplifier, it digitizes signals with the 0.3 LSB RMS transition noise floor preserving the dynamic range needed for FFT analysis. The 40-QFN package and DDR LVDS output enable high-density synchronized channel arrays on a single FPGA receiver, with deterministic latency supporting time-aligned beamforming.
Recommended
Software-Defined Radio Receiver
The LTC2256IUJ-12 works as a baseband digitizer in software-defined radio receivers where the 12-bit/25 MSPS combination is sufficient for narrowband amateur, ISM-band, or low-bandwidth commercial demodulation. Its 0.3 LSB RMS transition noise and configurable LVDS output pair well with FPGA digital downconverters, allowing demodulation of FM, AM, GMSK, and QPSK signals with software-reconfigurable channel bandwidth. The 1.8 V single-rail supply suits battery-powered QRP and portable SDR kits, and the 6x6 mm QFN footprint drops directly onto existing SDR front-end boards as a 12-bit replacement for legacy 8-bit converters.
Recommended
Industrial Vibration Monitoring
The LTC2256IUJ-12 is well matched to industrial vibration and condition-monitoring systems where 12-bit resolution is sufficient for envelope and bearing-fault detection analysis. The 25 MSPS rate over-samples vibration signals at typical 1-10 kHz frequencies by >1000x, providing substantial FFT dynamic range after windowing. Placed after an IEPE-compatible charge or piezo sensor amplifier, the digitizer feeds an FFT engine running envelope analysis for predictive maintenance. The 1.8 V supply and 6x6 mm QFN support battery-powered wireless sensor nodes, and the industrial temperature grade enables deployment in factory-floor cabinets without active cooling.
Recommended
Recommended Products Summary
Engineering reference data for LTC2256IUJ-12 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2257IUJ-12 | LTC2258IUJ-12 | LTC2256CUJ-12 | LTC2256IUJ-14 | LTC2265CUJ-12 |
|---|---|---|---|---|---|---|
| Package | 40-Lead QFN (6x6) with EP | 40-Lead QFN (6x6) with EP - same | 40-Lead QFN (6x6) with EP - same | 40-Lead QFN (6x6) with EP - same | 40-Lead QFN (6x6) with EP - same | 40-Lead QFN (6x6) with EP - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 14 bit | 12 bit |
| Sampling Rate | 25 MSPS | 40 MSPS | 65 MSPS | 25 MSPS | 25 MSPS | 65 MSPS |
| Analog Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Output Mode | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS |
| INL (typ) | ±0.3 LSB | ±0.3 LSB | ±0.3 LSB | ±0.3 LSB | ±1 LSB | ±0.3 LSB |
| Temperature Grade | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial (0C to +70C) |
Key Differentiators
- Lowest-power member of pin-compatible 25/40/65 MSPS ADC family (vs LTC2257IUJ-12 / LTC2258IUJ-12)
- Single 1.8 V analog supply simplifies power-tree design (vs LTC2220-12 (older 3.3 V family))
- Configurable CMOS/DDR CMOS/DDR LVDS output interface (vs LTC2256IUJ-12 vs single-mode 12-bit ADCs)
Design Notes
The LTC2256IUJ-12 operates from a single 1.8 V analog supply (AVDD) and a separate 1.2 V to 1.8 V output supply (OVDD). Estimated: at 25 MSPS the device draws approximately 30-40 mW from AVDD; place a 10 uF bulk + 0.1 uF ceramic decoupling capacitor as close to each AVDD pin as possible to suppress switching noise coupling into the analog front-end. Drive OVDD from the FPGA bank supply to avoid level-shifters.
Route the differential analog inputs (INA+/INA-) and clock (CLK+/CLK-) as length-matched 100 ohm differential pairs on the top layer over a continuous ground plane. Keep digital outputs (D0-D11 and SPI) on the opposite side of the package from the analog inputs to minimize coupling. Solder the exposed pad (EP) to a large, uninterrupted ground plane with multiple thermal vias to provide a low thermal resistance path and stable ground reference.
Do not drive CLK+ and CLK- with a single-ended clock source: a low-jitter differential clock (LVDS or PECL level) is required to meet the datasheet SNR. Drive the ADC input in fully-differential mode with a common-mode voltage of ~0.9 V (provided by the internal VCM buffer) for best linearity; single-ended drive degrades INL by 2-3x. The transition noise floor of 0.3 LSB RMS is only achieved with the internal reference bypassed at 0.1 uF + 10 uF.
For DDR LVDS output mode, route the data and DCO clock lines as 100 ohm differential pairs with length matching within 5 ps (about 0.8 mm). Source-terminate each pair near the ADC output pins with 100 ohm across the pair to prevent reflections. Keep the maximum trace length under 50 mm and avoid right-angle bends to preserve the 1-2 ns setup/hold window at the FPGA receiver.
Compliance Information
RoHS compliant per #PBF part suffix. Lead-free (Pb-free) construction. Not AEC-Q100 qualified - industrial and consumer use only. REACH compliance per Analog Devices product declarations.
