LTC2256CUJ-12 - 12-Bit 25Msps Ultralow Power 1.8V ADC | Analog Devices
MPN: LTC2256CUJ-12 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $27.5 | $27.50 |
| 10 | $24.75 | $247.50 |
| 100 | $21.8 | $2,180.00 |
| 500 | $19.4 | $9,700.00 |
| 1,000 | $17.2 | $17,200.00 |
LTC2256CUJ-12 Overview
What is an SAR/pipelined ADC? An analog-to-digital converter (ADC) translates continuous analog signals into discrete digital codes. The pipelined ADC architecture, used in the LTC2256CUJ-12, combines multiple low-resolution flash stages with digital error correction to deliver high sampling rates (tens to hundreds of MSPS) at moderate resolution (10-16 bit), suiting it to wideband communications, imaging, and instrumentation. Within the broader semiconductor hierarchy, the LTC2256CUJ-12 belongs to the data-converter family (ADC), which sits under mixed-signal ICs and interface ICs.
Key specifications include 0.17 ps RMS ultralow jitter for accurate IF undersampling, ±0.3 LSB INL (typical) and ±0.1 LSB DNL (typical) with no missing codes over temperature, and 0.3 LSB RMS transition noise. The digital outputs can be configured as full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS, with a separate output supply pin allowing the CMOS swing to range from 0.5 V to 1.8 V. The 1.8 V single-supply operation makes it well-suited to low-power, battery-friendly designs.
The architecture combines a front-end differential S/H, a multi-stage pipelined quantizer chain, and an internal bandgap reference, while supporting an optional external reference for noise-critical paths. AC performance - 71.1 dB SNR and 88 dB SFDR at 25 Msps - is preserved across input frequencies up to and beyond Nyquist, with sub-picosecond aperture jitter enabling accurate undersampling of IF signals commonly used in communications and radar systems.
Typical applications include cellular base-station receivers, IF digitizers in software-defined radio (SDR), medical imaging front-ends, handheld portable test equipment, and low-power instrumentation. The combination of 1.8 V single-supply operation, 25 Msps speed, and differential input makes it ideal for any signal chain where wide dynamic range and low power must coexist.
When designing in this part, use a multilayer PCB with a continuous unbroken ground plane and place the exposed pad on a thermal/ground copper pour. Decouple AVDD, DVDD, and OVDD with 10 uF and 0.1 uF ceramic capacitors placed as close to the pins as possible, and route differential analog inputs with matched impedance and length to preserve the rated SFDR. A separate OVDD supply lets you interface directly to 1.8 V logic without level shifters.
This page consolidates distributor stock, verified pin-compatible alternatives, and application guidance that goes beyond the manufacturer's datasheet so procurement and design engineers can decide quickly whether the LTC2256CUJ-12 fits their signal chain.
Drop-in alternatives for LTC2256CUJ-12 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2256CUJ-12 (same form factor and footprint) — differing in Package, RoHS Status, Resolution, Transition Noise, Data Interface.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2256IUJ-12#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2257CUJ-12#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2258CUJ-12#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2256CUJ-12#TRPBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2260CUJ-12#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2151CUJ-14#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2256CUJ-12 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bit |
| Sample Rate | 25 Msps |
| Architecture | Pipelined |
| Number of Channels | 1 |
| Input Type | Differential |
| Data Interface | Parallel CMOS / DDR CMOS / DDR LVDS |
| Analog Supply Voltage (AVDD) | 1.8 V (typ) |
| Power Consumption | 62 mW at 25 Msps |
| SNR | 71.1 dB |
| SFDR | 88 dB |
| INL (typical) | ±0.3 LSB |
| DNL (typical) | ±0.1 LSB |
| Transition Noise | 0.3 LSB RMS |
| Aperture Jitter | 0.17 ps RMS |
| Output Supply Range (OVDD) | 0.5 V to 1.8 V |
| Reference | Internal or external |
| Package | 40-QFN (6 x 6 mm) with exposed pad |
| Operating Temperature (Commercial, CUJ) | 0 C to +70 C |
| RoHS Status | Compliant (#PBF suffix) |
| Lead-Free | Yes (#PBF suffix) |
LTC2256CUJ-12 Pin Configuration
| Pin 1 | AIN+ — Differential analog input positive |
| Pin 2 | AIN- — Differential analog input negative |
| Pin 3 | VCM — Common-mode voltage output |
| Pin 4 | REFT — Reference top decoupling |
| Pin 5 | REFB — Reference bottom decoupling |
| Pin 6 | REFRTN — Reference return |
| Pin 7 | REFIN — Reference input / internal reference output |
| Pin 8 | SENSE — Reference mode select (internal/external) |
| Pin 9 | OGND — Output driver ground |
| Pin 10 | OVDD — Output driver supply |
| Pin 11 | D0 — Digital output bit 0 (LSB) |
| Pin 12 | D1 — Digital output bit 1 |
| Pin 13 | D2 — Digital output bit 2 |
| Pin 14 | D3 — Digital output bit 3 |
| Pin 15 | D4 — Digital output bit 4 |
| Pin 16 | D5 — Digital output bit 5 |
| Pin 17 | D6 — Digital output bit 6 |
| Pin 18 | D7 — Digital output bit 7 |
| Pin 19 | D8 — Digital output bit 8 |
| Pin 20 | D9 — Digital output bit 9 |
| Pin 21 | D10 — Digital output bit 10 |
| Pin 22 | D11 — Digital output bit 11 (MSB) |
| Pin 23 | NC — Not connected (per datasheet) |
| Pin 24 | OGND — Output driver ground |
| Pin 25 | OVDD — Output driver supply |
| Pin 26 | CLKOUT- — Differential clock output negative |
| Pin 27 | CLKOUT+ — Differential clock output positive |
| Pin 28 | CLK- — Differential clock input negative |
| Pin 29 | CLK+ — Differential clock input positive |
| Pin 30 | MODE — Output mode select (CMOS / DDR CMOS / DDR LVDS) |
| Pin 31 | OE — Output enable |
| Pin 32 | DGND — Digital ground |
| Pin 33 | DVDD — Digital 1.8 V supply |
| Pin 34 | AGND — Analog ground |
| Pin 35 | AVDD — Analog 1.8 V supply |
| Pin 36 | NC — Not connected (per datasheet) |
| Pin 37 | NC — Not connected (per datasheet) |
| Pin 38 | NC — Not connected (per datasheet) |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | EP — Exposed pad - thermal/ground connection |
Typical Applications
LTC2256CUJ-12 is suitable for 6 applications: Cellular Base-Station IF Digitizer, Software-Defined Radio (SDR) Receiver, Medical Imaging Front-End, Handheld Portable Test Equipment, Low-Power Industrial Instrumentation, Wideband Communication Signal Analyzer.
Cellular Base-Station IF Digitizer
The LTC2256CUJ-12 fits cellular base-station IF digitizers because its 25 Msps sample rate and 0.17 ps RMS aperture jitter let it undersample IF signals cleanly without aliasing artifacts. Its 71.1 dB SNR and 88 dB SFDR preserve signal integrity across multi-carrier GSM, LTE, and 5G NR waveforms, while 1.8 V single-supply operation reduces board-level power budget. Placed between the SAW filter and the FPGA baseband, the ADC drives parallel CMOS or DDR LVDS outputs directly to the FPGA SERDES, eliminating level shifters and shrinking BOM. The 40-QFN exposed pad provides a low-thermal-resistance path so the 62 mW dissipation is handled with a standard ground pour.
Recommended
Software-Defined Radio (SDR) Receiver
In software-defined radio receivers, the LTC2256CUJ-12 digitizes wideband IF blocks directly into the FPGA, where DSP performs channelization and demodulation. Its 0.17 ps RMS aperture jitter is below the phase-noise contribution of typical VCOs, so the SNR floor of 71.1 dB is dominated by the input signal rather than the ADC. The 1.8 V AVDD simplifies power-tree design in battery-powered manpack or handheld SDRs, and the DDR LVDS output mode minimizes FPGA pin count. Designers benefit from the same 40-QFN footprint as the higher-speed LTC2257-12 and LTC2258-12, allowing one PCB to serve multiple product tiers.
Recommended
Medical Imaging Front-End
Portable ultrasound and patient-monitoring front-ends use the LTC2256CUJ-12 to digitize conditioned analog signals at low power. With 71.1 dB SNR and only 62 mW dissipation, the ADC preserves diagnostic detail while keeping thermal rise inside sealed plastic enclosures minimal. The differential input rejects common-mode noise from long sensor cables and from nearby switching power supplies. The exposed-pad 40-QFN package makes thermal management straightforward in fan-less medical chassis, and the 0 C to +70 C commercial grade covers clinical-room deployments. For portable or field-use designs, designers step up to the LTC2256IUJ-12 industrial variant.
Recommended
Handheld Portable Test Equipment
Battery-powered oscilloscope probes, signal analyzers, and field-strength meters leverage the LTC2256CUJ-12 to digitize up to 10 MHz of input bandwidth while drawing only 62 mW. The 1.8 V AVDD simplifies USB or Li-Ion powered designs, and the parallel CMOS output mode lets low-cost microcontrollers or FPGAs capture samples without expensive LVDS hardware. The 88 dB SFDR is more than enough for spectrum-analyzer-grade amplitude accuracy, and the exposed-pad 40-QFN keeps the analog front-end thermally isolated from the digital section. Designers reusing the same PCB across speed grades can move up to the LTC2257CUJ-12 (40 Msps) or LTC2258CUJ-12 (65 Msps) without layout changes.
Recommended
Low-Power Industrial Instrumentation
Industrial vibration, acoustic, and process-control instruments use the LTC2256CUJ-12 to convert transducer outputs into digital streams with high dynamic range. The 12-bit resolution combined with 71.1 dB SNR lets designers detect small signals on top of large DC offsets, while the differential input rejects switching noise from motor drives and solenoid coils. The 1.8 V AVDD integrates cleanly with modern low-power MCUs, and the exposed-pad 40-QFN provides mechanical robustness for industrial enclosures. For deployments beyond 0 C to +70 C, designers migrate to the pin-compatible LTC2256IUJ-12 industrial-grade variant.
Recommended
Wideband Communication Signal Analyzer
The LTC2256CUJ-12 is a strong fit for wideband communication signal analyzers that need to capture moderate-bandwidth signals with high linearity. Its 88 dB SFDR ensures that harmonic and intermodulation artifacts stay well below the signal of interest, while the 0.17 ps RMS jitter guarantees that wideband noise does not degrade low-level spectral measurements. The DDR LVDS output mode drives modern FPGAs at full sample rate across short board traces, and the 1.8 V supply rail simplifies integration into mixed-signal analyzer backplanes. A common 40-QFN footprint with the LTC2257-12 and LTC2258-12 lets one hardware platform address 25/40/65 Msps product tiers.
Recommended
Recommended Products Summary
Engineering reference data for LTC2256CUJ-12 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2256IUJ-12#PBF | LTC2257CUJ-12#PBF | LTC2258CUJ-12#PBF | LTC2260CUJ-12#PBF | LTC2151CUJ-14#PBF |
|---|---|---|---|---|---|---|
| Package | 40-QFN (6x6) | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 14 bit | 14 bit |
| Analog Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Operating Temperature | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C |
| Differential Input | Yes | Yes | Yes | Yes | Yes | Yes |
Key Differentiators
- Lowest power in the 12-bit 25 Msps QFN-40 class (vs LTC2257CUJ-12#PBF)
- Pin-compatible upgrade path to 65 Msps (vs LTC2258CUJ-12#PBF)
- Sub-picosecond aperture jitter enables IF undersampling (vs LTC2260CUJ-12#PBF)
Design Notes
Use a multilayer PCB with a continuous, unbroken ground plane under the LTC2256CUJ-12 - per the Analog Devices datasheet recommendation. Place 10 uF and 0.1 uF ceramic decoupling capacitors on AVDD, DVDD, and OVDD as close to their respective pins as possible. The exposed pad (EP) must be soldered to a ground copper pour that is stitched with multiple vias to the inner ground plane to minimize thermal resistance and provide a low-inductance return path for the high-speed digital outputs.
Route the differential analog inputs (AIN+/AIN-) and differential clock (CLK+/CLK-) with matched trace lengths and 100 ohm differential impedance to preserve the rated 88 dB SFDR. Keep analog input traces away from the digital output bus and the OVDD supply; if the digital outputs are DDR LVDS, route them as a 100 ohm differential pair with a ground reference plane. Place the common-mode voltage output (VCM) bypass cap close to its pin to filter reference noise.
Do not leave OVDD floating - the output mode (CMOS, DDR CMOS, DDR LVDS) depends on a valid OVDD supply between 0.5 V and 1.8 V. Ensure MODE is tied to a logic-high or logic-low level through a 10 kohm resistor at the pin, not at the FPGA, to avoid reflections. If using the internal reference, the REFT and REFB pins each require a 2.2 uF X7R ceramic bypass; omitting these caps degrades SNR by several dB.
Compliance Information
Lead-free and RoHS compliant per the #PBF ordering suffix. AEC-Q100 is not applicable (commercial/industrial grade). Halogen-free status not explicitly stated in the verified data and marked unknown.
