MPC8360EVVAGDGA - PowerQUICC II Pro SoC, 400MHz, 740-TBGA | NXP
MPN: MPC8360EVVAGDGA ⚠ Last Time BuyMPC8360EVVAGDGA Overview
A communications SoC (System-on-Chip) is an integrated circuit that combines a microprocessor core, on-chip peripherals, memory controllers, and protocol-specific hardware accelerators (such as security engines and Ethernet MACs) onto a single silicon die, reducing board area and BOM cost compared to a discrete MPU plus external bridges. The MPC8360E PowerQUICC II Pro family is a next-generation extension of the PowerQUICC II line targeting routers, DSLAMs, media gateways, and industrial control platforms where one chip must terminate multiple telecom/ datacom protocols simultaneously.
Key features include the e300 core running at 400 MHz, integrated DDR1/DDR2 SDRAM controller with ECC, 32-bit PCI 2.2 interface, 32-bit/36-bit SEC (security engine) for IPSec/SSL offload, one tri-speed 10/100/1000 Mb/s Ethernet MAC, USB 2.0 host/device, TDM/H.110 interface, ATM SAR support, and a local bus controller. Operating voltage is 1.2 V core with 3.3 V I/O. The 0 to 105C ambient operating range suits commercial and industrial environments.
The MPC8360EVVAGDGA architecture separates the e300 core from the CPM (Communication Processor Module) co-processor that handles DMA and protocol termination in hardware, offloading packet processing from the main CPU. This dual-engine structure lets one chip sustain line-rate encryption (SEC) plus GbE bridging without saturating the core, which is the key reason PowerQUICC II Pro devices remain in service in long-life networking and industrial platforms.
Typical applications include SOHO routers, xDSL line cards, integrated access devices, media gateways, industrial control routers, and secure appliance controllers. Compared to MPC8358E devices the MPC8360E adds PCI-X and additional USB PHYs; compared to MPC8360EZU variants the EVVAGDGA retains all features with the specific 740-TBGA (37.5x37.5 mm) outline specified for this order code.
When designing with this part, allocate adequate PCB footprint for the 37.5x37.5 mm TBGA, keep DDR traces length-matched within the controller's published skew budget, and review the Rev 2.x hardware specification document for JTAG, reset, and PLL filtering guidance.
This page synthesizes distributor stock data, same-package MPC8360 variants, and practical hardware design notes not aggregated in any single manufacturer PDF.
Drop-in alternatives for MPC8360EVVAGDGA — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MPC8360EVVAGDGA (same form factor and footprint) — differing in Ethernet, PCI Interface, Series, USB, Mounting Type.
MPC8360EZUAGDGA
✅ Drop-InContact for price
View Datasheet →MPC8360EVVAGDG
✅ Drop-In📋 Reference alternative (not in catalog)
MPC8360EZUAGDG
✅ Drop-In📋 Reference alternative (not in catalog)
MPC8360VVAGDGA
✅ Drop-InContact for price
View Datasheet →MPC8360ZUAJDGA
✅ Drop-InContact for price
View Datasheet →MPC8360EVVAGDGA Maximum Ratings & Electrical Characteristics
| Core | Power Architecture e300 (enhanced MPC603e) |
| Number of Cores | 1 |
| Data Bus Width | 32-bit |
| Maximum Clock Frequency | 400 MHz |
| Operating Core Voltage | 1.2 V |
| I/O Voltage | 3.3 V |
| Memory Controller | DDR1/DDR2 SDRAM with ECC |
| PCI Interface | PCI 2.2 (32-bit, 66 MHz) / PCI-X |
| Ethernet | 1x 10/100/1000 Mb/s MAC (GMII/TBI/RGMII) |
| Security Engine | SEC (IPSEC/SSL/SRNG) |
| USB | USB 2.0 |
| TDM / H.110 | Yes |
| ATM Support | Yes (ATM SAR, AAL) |
| Operating Temperature Range | 0C to +105C (TA) |
| Package | 740-TBGA (37.5 x 37.5 mm) |
| Lead-Free | Yes (per distributor listing, Mouser 'NO-PB' coding) |
| Series | PowerQUICC II Pro (MPC8360E family) |
| Revision | Silicon Rev 1 (per distributor datasheet summary); Rev 2.x hardware specification referenced |
| Mounting Type | Surface Mount (TBGA ball grid) |
| Packaging | Tray |
| ECCN | 5A002.a.1 |
MPC8360EVVAGDGA Pin Configuration
| Pin A1 | VSS — Ground reference (multiple VSS balls, ball ID per BGA map) |
| Pin B1 | VDD — Core 1.2 V supply (multiple VDD balls, ball ID per BGA map) |
Typical Applications
MPC8360EVVAGDGA is suitable for 6 applications: Integrated Access Device / SOHO Router, xDSL Line Card / DSLAM, Secure Industrial Gateway, Media Gateway / VoIP Platform, Network-Attached Storage Controller, Secure Appliance / VPN Concentrator.
Integrated Access Device / SOHO Router
The MPC8360EVVAGDGA fits SOHO and branch-office integrated access devices because it terminates multiple WAN protocols on a single die. The e300 core runs routing and management daemons at 400 MHz while the CPM offloads ATM SAR, TDM, and Ethernet DMA. The integrated SEC engine performs line-rate IPSec/SSL for VPN tunnels, and the DDR1/DDR2 controller feeds packet buffers. A typical board uses one MPC8360EVVAGDGA, a 256 MB DDR2, a small NOR boot flash, and a 4-port Ethernet switch - replacing what would otherwise be a CPU plus three or four bridge ASICs.
Recommended
xDSL Line Card / DSLAM
Inside a DSLAM line card the MPC8360EVVAGDGA terminates ATM or PTM traffic from the DSL PHY, performs traffic shaping and policing in the CPM, then hands packets upstream over PCI or GbE. The 400 MHz e300 core has sufficient headroom for QoS queues and OAM processing, while the SEC engine accelerates the IPSec required by remote-management tunnels. The 740-TBGA is footprint-compatible with the broader MPC8360E family, allowing line-card variants (with different feature gating) to share one PCB layout across SKUs.
Recommended
Secure Industrial Gateway
For industrial sites that require a hardened gateway between field buses (Modbus, Profibus, CAN) and the enterprise network, the MPC8360EVVAGDGA is attractive because the SEC engine provides hardware VPN, the e300 core runs the SCADA/server stack, and the on-chip Ethernet + TDM simplify dual-network attachment. Industrial-grade mezzanine cards typically expose isolated serial ports to the MPC8360's UARTs and route encrypted traffic over the GbE MAC. The 0 to 105C operating range suits most cabinet environments.
Recommended
Media Gateway / VoIP Platform
VoIP and unified-communications media gateways use the MPC8360EVVAGDGA's TDM/H.110 interface to bridge legacy PSTN T1/E1 trunks to IP, while the e300 core runs SIP/RTP stacks. The CPM's multi-channel DMA and ATM SAR offload time-critical DSP packet handling. DDR2 memory supplies buffer space for jitter buffers and voice recordings. A four-port BRI gateway can be built around one MPC8360EVVAGDGA plus quad TDM framer devices on the local bus.
Recommended
Network-Attached Storage Controller
Although positioned as a communications SoC, the MPC8360EVVAGDGA is also used in entry-level NAS controllers where the PCI-X bus attaches SATA or RAID HBAs and the e300 core runs the storage stack. DDR2 provides cache memory, the SEC engine handles encrypted-volume offload (CBC-AES), and the GbE MAC serves the network side. Designers favor the part for long-life industrial/embedded NAS appliances where other QorIQ parts are overspec.
Recommended
Secure Appliance / VPN Concentrator
Small-form-factor VPN concentrators and secure appliances leverage the MPC8360EVVAGDGA's SEC engine to sustain line-rate AES-256/SHA-1 IPSec tunnels on the GbE port. The e300 core handles IKE key exchange and policy management, while the DDR2 controller supplies the policy and SA-cache tables. Because the SEC offload is hardware, total tunnel count scales with packet size rather than CPU frequency, which is a key advantage over soft-crypto implementations.
Recommended
Recommended Products Summary
Engineering reference data for MPC8360EVVAGDGA — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MPC8360EZUAGDGA | MPC8360EVVAGDG | MPC8360EZUAGDG | MPC8360VVAGDGA | MPC8360ZUAJDGA |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 740-TBGA (37.5x37.5 mm) | 740-TBGA (37.5x37.5 mm) | 740-TBGA (37.5x37.5 mm) | 740-TBGA (37.5x37.5 mm) | 740-TBGA (37.5x37.5 mm) | 740-TBGA (37.5x37.5 mm) |
| Core | e300 @ 400 MHz | e300 @ 400 MHz | e300 @ 400 MHz | e300 @ 400 MHz | e300 @ 400 MHz | e300 @ 400 MHz |
| Security Engine | SEC (full crypto + RNG) | SEC (full crypto + RNG) | SEC (full crypto + RNG) | SEC (full crypto + RNG) | Reduced / disabled | SEC enabled |
| USB | USB 2.0 | USB 2.0 | USB 2.0 | USB 2.0 | USB 2.0 | USB 2.0 |
| Feature Gating Suffix Code | EVV | EZU | EVV | EZU | VV | ZUAJ |
| Lead Free / RoHS | Lead Free (NO-PB) | Lead Free | Lead Free | Lead Free | Lead Free | Lead Free |
| Operating Temperature | 0C to +105C | 0C to +105C | 0C to +105C | 0C to +105C | 0C to +105C | 0C to +105C (junction grade) |
Key Differentiators
- Full SEC crypto engine with RNG/SRNG and IPSec/SSL offload (vs MPC8360VVAGDGA)
- Wider feature gating with USB 2.0, PCI-X, ATM SAR, and 1 GbE all enabled (vs MPC8358E)
- Same 740-TBGA outline enabling layout reuse across the entire family (vs QorIQ MPC8536E (TeMAP/TBGA package, different outline))
Design Notes
The 740-TBGA at 37.5 x 37.5 mm requires a 6-layer (or 8-layer) PCB with dedicated ground and power planes under the BGA field. Match DDR traces to within the controller's published skew budget (typically +/- 25 ps), keep reference-plane transitions to a minimum, and place VTT termination dividers within 100 ps of the byte lane. The lead-free (NO-PB) ball finish requires SAC305 or equivalent lead-free reflow profiles (peak 245-260C).
The e300 core at 400 MHz draws substantial current on the 1.2 V rail; a multi-phase switching regulator with at least 20 A peak capability is recommended, plus 470 uF bulk + 22 uF ceramic + 100 nF high-frequency bypass per the manufacturer's decap recommendations. The 3.3 V I/O rail must be sequenced to the 1.2 V rail; refer to the hardware specification for the supported power-up order. PLL analog supply requires RC filtering within 10 mm of the AVSS pin.
Estimated: at 1.2 V core and 400 MHz with SEC + GbE + USB active, the part can dissipate 4-6 W. With a TBGA-attached thermal pad (or no thermal pad, depending on bond-revision), junction-to-ambient theta_JA is approximately 12-18 C/W on a 6-layer JEDEC test board; at 0C ambient this leaves considerable headroom, but at 105C ambient the margin shrinks. Provide at least 4 thermal vias-in-pad under the central BGA cluster if the silicon offers a thermal pad in your revision.
Watch for silicon revision notes: Rev 1 silicon has known errata in early USB and ECC masks; the Hardware Specification published for Rev 2.x lists workarounds. Always read the errata for your bonded revision before committing to boot code. Confirm the trailing 'A' in the order code matches the tray packaging; missing 'A' suffix variants exist with different packing quantities.
Compliance Information
Lead Free (NO-PB) per Mouser listing. Halogen Free per Globalspec cross-reference aggregator. RoHS compliance claimed at family level; specific certificate [DATA_NEEDED: RoHS document number for MPC8360EVVAGDGA]. Not AEC-Q100 qualified - this is a commercial/industrial communications processor, not automotive-grade.