MPC875ZT80 - PowerQUICC 80MHz 32-Bit MPU, 256-PBGA | NXP
MPN: MPC875ZT80 ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $48.5 | $48.50 |
| 10 | $42.1 | $421.00 |
| 100 | $36.75 | $3,675.00 |
| 500 | $31.2 | $15,600.00 |
| 1,000 | $26.4 | $26,400.00 |
MPC875ZT80 Overview
The PowerQUICC MPC8xx family represents a class of integrated communications processors that combine a Power Architecture CPU core with system integration units (SIU), communications processor module (CPM), and memory controllers on one die. These processors sit within the broader hierarchy of microprocessors -> embedded processors -> communications processors -> networking ASICs, and they historically powered routers, DSLAMs, and telecom infrastructure.
Key features of the MPC875ZT80 include the 32-bit Power Architecture core at 80 MHz, integrated CPM supporting common serial protocols, dual UART, HDLC, and PCI interface options. The device also integrates timers, a memory controller for SDRAM/ROM/SRAM, and a flexible system bus. Compared with discrete CPU-plus-comm-controller solutions, the MPC875ZT80 reduces board area and BOM cost by integrating the communications engine and the CPU on the same silicon.
The architecture uses a unified internal bus to couple the CPU core, CPM, and memory controller. The CPM offloads protocol processing from the CPU, allowing the Power Architecture core to focus on control-plane and management tasks. This dual-engine approach was pioneering for its era and influenced later PowerQUICC II/III designs. The integrated SIU manages pin multiplexing, interrupts, and reset configuration.
Typical applications include SOHO routers, ADSL/VDSL modems, Ethernet switches, industrial gateways, and legacy telecom equipment where deterministic communications performance and Power Architecture toolchain support matter more than raw MHz. The wide operating temperature range and integrated peripherals make the part suitable for embedded networking and factory automation gateways.
When designing with the MPC875ZT80, designers must plan for a 3.3V core/IO supply and external SDRAM. Boot configuration straps are read on reset and must be set via pull-up/pull-down resistors on the configuration pins. Thermal management relies primarily on the PBGA thermal pad - use sufficient ground vias and copper pours to keep junction temperature within limits.
This page consolidates distributor availability, drop-in pin-compatible alternatives (within the same MPC8xx family), and practical design notes beyond what the manufacturer datasheet provides, making it useful for engineers sustaining older designs or sourcing replacement inventory.
Drop-in alternatives for MPC875ZT80 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MPC875ZT80 (same form factor and footprint) — differing in Package, Mounting Type, Core Architecture, Data Bus Width, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MPC875VR80
✅ Drop-In📋 Reference alternative (not in catalog)
MPC870VR80
✅ Drop-In✓ In Stock
$20.1 / Unit
View Datasheet →MPC875ZT80 Maximum Ratings & Electrical Characteristics
| Architecture | Power Architecture (MPC8xx / PowerQUICC) |
| Core Count | 1 |
| Data Bus Width | 32-bit |
| Maximum Clock Frequency | 80 MHz |
| Package | 256-PBGA (23x23 mm) |
| Operating Temperature Range | 0 C to 95 C |
| Series | MPC8xx / PowerQUICC |
| Supply Voltage | 3.3 V (core/IO) |
| Mounting Type | Surface Mount |
| Integrated Peripherals | CPM (communications processor module), SIU, timers, UARTs, HDLC, PCI |
| Family Position | MPC8xx / PowerQUICC I |
MPC875ZT80 256-pbga (23x23 mm) Pin Configuration Guide
Pin configuration for MPC875ZT80 (256-pbga (23x23 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for MPC875ZT80.
Refer to the datasheet for full pin configuration.
Typical Applications
MPC875ZT80 is suitable for 6 applications: SOHO Routers and Gateways, ADSL / VDSL Modem Termination, Industrial Ethernet Switches, Legacy Telecom Equipment (T1/E1), Printers and Imaging Controllers, Embedded Data Concentrators.
SOHO Routers and Gateways
The MPC875ZT80's integrated CPM (communications processor module) handles Ethernet MAC, HDLC, and serial channels directly, offloading the Power Architecture core from packet processing. At 80 MHz with on-chip peripherals, it can manage routing tables, NAT, and basic QoS for SOHO broadband gateways without an external communication controller. Designers typically pair the MPC875ZT80 with an SDRAM bank and a small Flash for firmware, building a compact SOHO router on a 4-layer PCB.
Recommended
ADSL / VDSL Modem Termination
DSLAM line cards and customer-premises DSL modems historically relied on the MPC875's HDLC channels, UARTs, and PCI interface for interfacing to the PHY and ATM segmentation/reassembly blocks. The MPC875ZT80's 80 MHz CPU throughput is sufficient for PPPoE encapsulation, ATM AAL5, and basic traffic shaping at DSL data rates. The 256-PBGA package's thermal pad allows sustained operation under continuous data flow typical of always-on DSL links.
Recommended
Industrial Ethernet Switches
The MPC875ZT80 integrates PCI, dual UART, and HDLC channels useful for managed industrial Ethernet switches handling PROFINET, EtherNet/IP, or Modbus TCP traffic. Its CPM offloads time-critical protocol handling from the CPU, leaving the Power Architecture core to run the management stack, web interface, and diagnostics. The 0-95 C commercial temperature range covers most factory-floor environments inside control cabinets.
Recommended
Legacy Telecom Equipment (T1/E1)
The MPC875ZT80's HDLC controllers and TDM support make it well-suited for legacy T1/E1 channel banks, PBX line cards, and frame-relay access devices still in service today. The integrated CPM handles per-channel HDLC framing at T1 (1.544 Mbps) and E1 (2.048 Mbps) line rates without external glue logic. Telecom OEMs who designed with PowerQUICC I in the late 1990s and early 2000s continue to source MPC875ZT80 for sustaining spare-part production.
Recommended
Printers and Imaging Controllers
Networked multifunction printers in the early 2000s used the MPC875ZT80 as a print-server and scanner controller, leveraging its PCI bus to connect to image-processing ASICs and its Ethernet MAC for network connectivity. The Power Architecture core runs the embedded OS and page-description-language interpreters, while the CPM manages the network side. This role has largely been replaced by integrated SoCs, but legacy MFPs and industrial label printers continue to use the MPC875ZT80.
Recommended
Embedded Data Concentrators
In remote-terminal units (RTUs) and SCADA data concentrators, the MPC875ZT80 aggregates serial sensor data from RS-485/RS-232 links via its integrated UARTs and forwards them upstream over Ethernet. The CPM's DMA channels efficiently move serial data into memory, while the CPU handles protocol conversion (Modbus, DNP3). With 32-bit processing and on-chip peripherals, the MPC875ZT80 replaces multiple discrete microcontrollers and protocol converters in compact data-concentrator designs.
Recommended
Recommended Products Summary
Engineering reference data for MPC875ZT80 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MPC875VR80 | MPC870VR80 |
|---|---|---|---|
| Brand | NXP Semiconductors (formerly Freescale) | NXP Semiconductors | NXP Semiconductors |
| Package | 256-PBGA (23x23 mm) | 256-PBGA (23x23 mm) - same | 256-PBGA (23x23 mm) - same |
| Architecture | Power Architecture (MPC8xx / PowerQUICC I) | Power Architecture (MPC8xx / PowerQUICC I) | Power Architecture (MPC8xx / PowerQUICC I) |
| Maximum Clock Frequency | 80 MHz | 80 MHz | 80 MHz |
| Core Count | 1 | 1 | 1 |
| Data Bus Width | 32-bit | 32-bit | 32-bit |
| Operating Temperature Range | 0 C to +95 C (commercial) | -40 C to +105 C (industrial) | -40 C to +105 C (industrial) |
| Integrated Peripherals (CPM/SIU) | Full CPM: HDLC, UART, PCI, timers | Full CPM (matches MPC875ZT80) | Reduced CPM (fewer serial channels than MPC875) |
| Lifecycle Status | Last-time-buy / EOL | Last-time-buy / EOL | Last-time-buy / EOL |
Key Differentiators
- Integrated CPM offloads serial-protocol processing (vs MPC870VR80)
- Commercial temperature grade screened at 80 MHz (vs MPC875VR80)
- Direct NXP/Freescale drop-in within same 256-PBGA footprint (vs PowerQUICC II (MPC82xx))
Design Notes
The MPC875ZT80 requires a stable 3.3V supply for both core and I/O rails. Place 10 uF tantalum plus 0.1 uF ceramic decoupling capacitors close to each PBGA power pin pair, and use a wide power plane to limit voltage drop during CPM DMA bursts. The PLL supply (VCCSYN) should be filtered with a ferrite bead and decoupled with 10 uF + 0.1 uF to minimise jitter on the 80 MHz system clock.
Estimated: at 80 MHz with continuous CPM activity, the MPC875ZT80 dissipates approximately 1.0-1.5 W into the 256-PBGA thermal pad. Use a 6x6 via array (0.3 mm drill, 0.6 mm pitch) under the thermal pad stitched to an internal ground plane to keep junction temperature within the 95 C commercial limit. Avoid placing the part near board edges where thermal relief is poor.
Route SDRAM address and data traces with matched lengths (within +/- 1 cm) to preserve timing margins at 80 MHz. Keep CPM serial clocks away from analog or reset traces to avoid coupling. Place the boot-configuration pull-up/pull-down resistors within 5 mm of the configuration pins so reset behaviour is unambiguous.
Do not confuse MPC875 (PowerQUICC I) with MPC827x (PowerQUICC II): they share the Power Architecture heritage but have different bus architectures, peripheral sets, and pinouts. Migration between the two families requires PCB redesign. Also note that the 'Z' suffix on MPC875ZT80 indicates 80 MHz commercial-temperature grade - selecting the wrong temperature grade invalidates timing specs.
Compliance Information
Detailed compliance data not present in the verified web snippets; refer to the NXP product-change-notice page and the manufacturer datasheet for definitive RoHS/lead-free/reach status of the specific date/lot code on hand.