N25Q128A13ESF40G-TR - 128Mb Serial NOR Flash, 108MHz SPI, SOIC-16 | Micron
MPN: N25Q128A13ESF40G-TR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1.95 | $1.95 |
| 10 | $1.62 | $16.20 |
| 100 | $1.18 | $118.00 |
| 500 | $0.92 | $460.00 |
| 1,000 | $0.78 | $780.00 |
| 2,500 | $0.66 | $1,650.00 |
N25Q128A13ESF40G-TR Overview
A serial NOR flash is a non-volatile memory device that uses a low-pin-count synchronous serial interface (SPI) rather than a wide parallel bus. In the broader memory hierarchy, NOR flash sits at the same tier as parallel NOR for code storage but trades bus width for footprint savings; serial NOR is the dominant choice on modern microcontrollers and SoCs that lack an external memory bus. The N25Q128 family implements the JEDEC-standard Serial Peripheral Interface with extensions for Dual SPI and Quad SPI, plus an optional serial command subset for JEDEC xSPI-compatible reads.
Key features include 128-Mbit density in 1/2/4-bit modes, 4-Kbyte uniform subsectors with 64-Kbyte sectors and 256-byte page programming buffer, top or bottom boot-block configuration, and security enhancements including one-time-programmable (OTP) protection, 3x 256-byte security registers, and a 64-bit unique ID. Program/erase endurance is rated at 100K cycles per sector minimum with 20-year data retention. The Quad SPI interface enables effective throughput up to 432 Mbit/s when all four I/O lines are active, comfortably supporting XiP code execution from flash on mid-range ARM Cortex-M and RISC-V SoCs.
Typical applications include firmware storage for IoT gateways, asset-tracking modules, and industrial controllers; data logging in metering and predictive-maintenance systems; boot ROM plus user-data storage in FPGA-based designs; and BIOS/UEFI storage on SBCs and embedded boards. The wide SOIC-16 footprint suits hand-soldered prototypes as well as high-volume SMT lines.
When designing with the N25Q128A13ESF40G-TR, observe the 108 MHz VCC/IO decoupling requirement by placing a 0.1 uF ceramic capacitor adjacent to pins 8 (VCC) and 16 (VSS). Quad SPI traces should be length-matched within approximately 25 mm to preserve sampling margin at 108 MHz, and a pull-up on the HOLD#/RESET# pin prevents unintended resets during power-rail ramp. The standard SPI command set is JEDEC-compatible, so most MCU HAL drivers work without modification.
This page synthesizes distributor pricing, drop-in alternatives, and design notes not found on standalone datasheet mirrors. Pricing was captured from authorized distributors as of 2026-10-05; all pinout and timing references should be reconfirmed against the manufacturer datasheet before PCB release.
Drop-in alternatives for N25Q128A13ESF40G-TR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with N25Q128A13ESF40G-TR (same form factor and footprint) — differing in Bus Interface, Data Retention, Memory Type, Operating Temperature, Package.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
N25Q128A13ESF40F-TR
✅ Drop-In📋 Reference alternative (not in catalog)
N25Q128A13ESF40E
✅ Drop-In📋 Reference alternative (not in catalog)
N25Q128A13ESF40G
✅ Drop-In✓ In Stock
$0.68 / Unit
View Datasheet →N25Q128A13ESFH0E-TR
✅ Drop-In📋 Reference alternative (not in catalog)
N25Q128A11ESF40G
✅ Drop-In📋 Reference alternative (not in catalog)
W25Q128JVSIQ
✅ Drop-In📋 Reference alternative (not in catalog)
MX25L12835FM2I-10G
✅ Drop-In📋 Reference alternative (not in catalog)
N25Q128A13ESF40G-TR Maximum Ratings & Electrical Characteristics
| Memory Type | Non-volatile NOR Flash (Serial) |
| Density | 128 Mbit (16 Mbyte) |
| Memory Organization | 128M/64M/32M x 1-bit / 2-bit / 4-bit |
| Bus Interface | SPI (Single, Dual, Quad SPI) |
| Max Clock Frequency | 108 MHz |
| Supply Voltage (VCC) | 2.7 V to 3.6 V (3.0 V typical 3V part) |
| Access Time (tACC) | 7 ns |
| Sector Erase Size | 4 Kbyte subsector, 64 Kbyte sector |
| Page Program Size | 256 byte |
| Program/Erase Endurance | 100,000 cycles per sector minimum |
| Data Retention | 20 years minimum |
| Operating Temperature | -40 C to +85 C |
| Package | 16-pin SOIC (SO) wide-body |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead-Free | Yes |
N25Q128A13ESF40G-TR Pin Configuration
| Pin 1 | CS# — Chip Select input, active low |
| Pin 2 | SO — Serial Data Output (MISO) / IO1 in Quad SPI mode |
| Pin 3 | WP# — Write Protect, active low; IO2 in Quad SPI mode |
| Pin 4 | GND — Ground reference |
| Pin 5 | SI — Serial Data Input (MOSI) / IO0 in Quad SPI mode |
| Pin 6 | SCK — Serial Clock input |
| Pin 7 | HOLD#/RESET# — Hold or Reset input, active low; IO3 in Quad SPI mode |
| Pin 8 | VCC — Power supply, 2.7 V to 3.6 V |
| Pin 9 | NC — Not connected (per datasheet) |
| Pin 10 | NC — Not connected (per datasheet) |
| Pin 11 | NC — Not connected (per datasheet) |
| Pin 12 | NC — Not connected (per datasheet) |
| Pin 13 | NC — Not connected (per datasheet) |
| Pin 14 | NC — Not connected (per datasheet) |
| Pin 15 | NC — Not connected (per datasheet) |
| Pin 16 | VSS — Ground reference |
Typical Applications
N25Q128A13ESF40G-TR is suitable for 6 applications: IoT Gateway Firmware Storage, Industrial Data Logging, FPGA Configuration Memory, Asset Tracking Modules, SBC BIOS/UEFI Storage, Medical Device Code Storage.
IoT Gateway Firmware Storage
The N25Q128A13ESF40G-TR's 128-Mbit density provides ample room for multi-image OTA firmware plus persistent configuration on IoT gateways. Its 108 MHz Quad SPI interface supports XiP code execution from a connected Cortex-M or RISC-V host, allowing the gateway to boot directly from flash without shadowing to RAM. The 100K-cycle erase endurance and 20-year retention meet the typical 7-10 year IoT deployment lifecycle. Place 0.1 uF decoupling adjacent to pins 8 (VCC) and 16 (VSS), and use 25 mm length-matched Quad SPI traces to preserve 108 MHz sampling margin.
Recommended
Industrial Data Logging
Predictive-maintenance and metering systems require non-volatile storage of vibration, temperature, and event logs that survive power cycling. The N25Q128A13ESF40G-TR offers 16 Mbyte of storage, 4-Kbyte subsector erase for selective log rotation, and 100K-cycle endurance suitable for multi-year continuous logging at sector-update rates typical of metering applications. The wide -40 C to +85 C industrial temperature range supports factory-floor and outdoor cabinet installations. Use the 256-byte page buffer for efficient burst logging, and consider dual-image storage to support fail-safe firmware rollback.
Recommended
FPGA Configuration Memory
Modern FPGAs and SoCs use external serial NOR as the primary configuration image store, replacing older parallel NOR and Platform Flash. The N25Q128A13ESF40G-TR pairs naturally with mid-range FPGAs such as Lattice ECP5, Xilinx Spartan-7, and Microsemi PolarFire, providing 128 Mbit of multi-boot image storage. Its 108 MHz Quad SPI throughput minimizes FPGA configuration time, and the package's standard 16-pin SOIC wide-body footprint is compatible with most FPGA dev kits. For multi-image fallback, use the 4-Kbyte subsector granularity to manage golden-image storage alongside the active bitstream.
Recommended
Asset Tracking Modules
Battery-powered asset-tracking modules need reliable, low-power non-volatile memory to store GPS waypoints, sensor telemetry, and BLE pairing information. The N25Q128A13ESF40G-TR's deep power-down current (~1 uA typical) preserves battery life, and its 128-Mbit density supports months of telemetry at typical sampling rates. Quad SPI enables fast bulk-log dump when the device returns to a charger cradle. Industrial temperature grading supports outdoor deployments in pallet tracking and cold-chain monitoring. Recommend pairing with a low-power BLE SoC such as the nRF52840 or a LoRa transceiver for long-range asset visibility.
Recommended
SBC BIOS/UEFI Storage
Single-board computers and embedded motherboards require a non-volatile boot ROM for BIOS, UEFI, bootloader, and recovery images. The N25Q128A13ESF40G-TR's 128-Mbit density stores a full UEFI firmware plus an A/B recovery partition in the same SOIC-16 footprint. Its 108 MHz Quad SPI bus allows sub-second cold-boot times on x86 boards that map SPI flash into the legacy BIOS memory window. Hardware write-protect via the WP# pin and the top/bottom boot-block options add a layer of tamper resistance suitable for embedded appliances.
Recommended
Medical Device Code Storage
Medical devices such as portable infusion pumps, patient monitors, and diagnostic instruments rely on deterministic firmware execution. The N25Q128A13ESF40G-TR's XiP capability lets a Cortex-M host fetch validated code directly from flash, simplifying IEC 62304 and FDA 21 CFR 820 compliance audits. The 100K-cycle endurance and 20-year retention support the typical 8-10 year medical-device lifecycle. Three 256-byte OTP security registers and a 64-bit unique ID enable per-device authentication, supporting anti-counterfeit controls required by medical device manufacturers.
Recommended
Recommended Products Summary
Engineering reference data for N25Q128A13ESF40G-TR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | N25Q128A13ESF40F-TR | N25Q128A13ESF40E | N25Q128A11ESF40G | W25Q128JVSIQ | MX25L12835FM2I-10G |
|---|---|---|---|---|---|---|
| Brand | Micron | Micron | Micron | Micron | Winbond | Macronix |
| Package | 16-pin SOIC (SO) wide-body | 16-pin SOIC (SO) wide-body - same | 16-pin SOIC (SO) wide-body - same | 16-pin SOIC (SO) wide-body - same | 16-pin SOIC (SO) wide-body - same | 16-pin SOIC (SO) wide-body - same |
| Density | 128 Mbit (16 Mbyte) | 128 Mbit | 128 Mbit | 128 Mbit | 128 Mbit | 128 Mbit |
| Max SPI Clock | 108 MHz | 108 MHz | 108 MHz | 108 MHz | 133 MHz | 104 MHz |
| Supply Voltage | 2.7 V to 3.6 V (3V) | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V | 2.7 V to 3.6 V |
| Subsector Erase Size | 4 Kbyte | 4 Kbyte | 4 Kbyte | 4 Kbyte | 4 Kbyte | 4 Kbyte |
| P/E Endurance | 100K cycles min | 100K cycles min | 100K cycles min | 100K cycles min | 100K cycles min | 100K cycles min |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| XiP Support | Yes | Yes | Yes | Yes | Yes | Yes |
| Packaging Variant | Tape & Reel (TR) | Tape & Reel (TR) | Tray (E variant) | Tube | Tape & Reel | Tape & Reel |
Key Differentiators
- A13 family with enhanced security and command-set extensions (vs N25Q128A11ESF40G)
- 108 MHz Quad SPI with XiP support on a 65nm NOR process (vs W25Q128JVSIQ)
- Wide-body SOIC-16 footprint for high-volume SMT (vs MX25L12835FM2I-10G)
Design Notes
Place a 0.1 uF X7R ceramic decoupling capacitor adjacent to pins 8 (VCC) and 16 (VSS), with the loop kept under 2 mm to minimize supply ripple during Quad SPI reads. For boards with high-speed hosts, add a 10 uF bulk capacitor near the flash footprint. Hold# and WP# should each be tied to VCC through a 10 kohm pull-up resistor to prevent unintended assertion during power-rail ramp.
Route the Quad SPI signals (SCK, CS#, IO0-IO3) as a length-matched group, ideally within 25 mm of each other, on the top layer over a continuous ground plane. Avoid vias in the Quad SPI traces; if unavoidable, keep them matched. Place the flash at least 5 mm away from noisy sources like DC-DC converters or switching FETs. Refer to the Micron Quad SPI layout application note for exact stack-up recommendations.
At 108 MHz SPI clock, signal integrity dominates over timing budget. Source-terminate SCK with a 33 ohm series resistor if the trace length exceeds 50 mm or if reflections appear on the scope. Verify setup/hold timing on a 4-channel scope using a fast active probe; for board bring-up, run the flash at 54 MHz first, then step to 108 MHz after confirming clean eyes. Quad SPI mode should not be enabled until timing margin is verified.
Do not leave HOLD#/RESET# floating - a noisy edge during power-up can put the device into reset. Verify the JEDEC ID at boot and after each brown-out to detect unintended state changes. When implementing OTA updates, lock the status register before issuing page-program operations to prevent accidental write-protect clears. The subsector erase is 4 Kbyte; ensure your firmware update logic issues 4-Kbyte aligned erases to avoid corrupting adjacent sectors.
Compliance Information
RoHS and lead-free status confirmed per Micron product page; AEC-Q100 not applicable for memory ICs.
