NVT2002DP,118 - 2-Bit Bidirectional Level Translator 1.0-5V | NXP
MPN: NVT2002DP,118 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0.38 | $0.38 |
| 10 | $0.34 | $3.40 |
| 100 | $0.29 | $29.00 |
| 500 | $0.24 | $120.00 |
| 1,000 | $0.19 | $190.00 |
NVT2002DP,118 Overview
A voltage level translator (also called a level shifter or voltage translator) is a mixed-signal interface IC that safely connects digital devices operating at different supply voltages, such as a 1.8 V microcontroller and a 5 V sensor. Level translators sit within the broader hierarchy of logic ICs and interface ICs in the signal chain, forming a bridge between voltage domains in power management and system I/O design. Without translation, direct connection risks over-voltage damage or failure to meet logic thresholds.
Key features of the NVT2002 include direction-pin-free operation, which simplifies control firmware and eliminates bus contention logic; support for both open-drain and push-pull applications; identical electrical characteristics across both channels with minimal output-to-output deviation; and low effective line capacitance for signal speeds below 33 MHz in open-drain mode. The architecture uses reference voltages Vref(A) and Vref(B) with an enable (EN) input that, when LOW, places all I/O in the high-impedance state, significantly reducing supply current.
Technically, the NVT2002 employs a pass-gate architecture: a one-shot edge accelerator briefly lowers the output impedance on rising edges to overcome the RC time constant of the pull-up resistors, while a bias network between Vref(B) and Vref(A) holds the bus near the A-side threshold. This hybrid approach combines the bidirectionality of open-drain schemes with the low capacitance and speed of transistor-switch designs, avoiding the propagation-delay penalty of dual-supply CMOS translators.
Typical applications include I2C, SMBus, and PMBus level shifting between 3.3 V controllers and 5 V peripherals, GPIO and UART interface translation in mixed-voltage embedded systems, and low-speed bus bridging in industrial and automotive body-electronics modules where microcontrollers such as NXP and ST MCUs interface to 5 V sensors and actuators.
One key design consideration: because the translator is open-drain at its core, push-pull operation requires proper pull-up resistor sizing - lower values improve edge rates but increase static current through the internal bias network, so engineers must trade speed against power consumption.
This page synthesizes distributor pricing, drop-in alternatives, practical design notes, and an application-by-application selection guide not found in the manufacturer datasheet, verified as of 2026-10-19.
Drop-in alternatives for NVT2002DP,118 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with NVT2002DP,118 (same form factor and footprint) — differing in Package.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
PCA9306DP,118
✅ Drop-In📋 Reference alternative (not in catalog)
GTL2002DP,118
✅ Drop-In📋 Reference alternative (not in catalog)
NVT2002GM,125
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
NVT2002DP,118 Specifications
| Translator Type | Bidirectional voltage level translator |
| Circuit | 1 circuit, 2 channels |
| A-Side Voltage Range (Vref(A)) | 1.0 V to 3.6 V |
| B-Side Voltage Range (Vref(B)) | 1.8 V to 5.5 V |
| Translation Range | 1.0 V to 5 V |
| Direction Control | No direction pin required |
| Application Mode | Open-drain and push-pull |
| Max Open-Drain Data Rate | < 33 MHz |
| Enable Input | EN, active HIGH (LOW = high-impedance I/O) |
| Channel-to-Channel Matching | All channels same electrical characteristics, minimal deviation |
| Package | TSSOP-8 (DP) |
| Mounting Type | Surface Mount |
| Reel Ordering Code Suffix | ,118 (standard packing) |
NVT2002DP,118 Pin Configuration
| Pin 1 | Vref(A) — A-side reference voltage, 1.0 V to 3.6 V |
| Pin 2 | A1 — A-side data I/O, channel 1 |
| Pin 3 | A2 — A-side data I/O, channel 2 |
| Pin 4 | GND — Ground (0 V) |
| Pin 5 | B2 — B-side data I/O, channel 2 |
| Pin 6 | B1 — B-side data I/O, channel 1 |
| Pin 7 | EN — Enable input; HIGH = translation active, LOW = all I/O high-impedance |
| Pin 8 | Vref(B) — B-side reference voltage, 1.8 V to 5.5 V |
Typical Applications
NVT2002DP,118 is suitable for 6 applications: I2C Bus Level Shifting, Mixed-Voltage GPIO Interfacing, SMBus and PMBus Power-System Management, Automotive Body Electronics and Gateways, UART and Low-Speed Serial Link Translation, 1-Wire and Single-Channel Open-Drain Buses.
I2C Bus Level Shifting
The NVT2002DP,118 is a natural fit for I2C level shifting because SDA and SCL are exactly two bidirectional open-drain lines - matching the part's 2-channel configuration precisely. With Vref(A) tied to a 1.8 V or 3.3 V controller rail and Vref(B) tied to a 5 V peripheral rail, the translator passes both logic levels without a direction pin, preserving clock stretching and multi-master arbitration. Its open-drain core means no bus contention logic or firmware handshake is needed. The internal one-shot edge accelerator restores sharp rising edges against pull-up RC loads, supporting standard 100 kHz and fast-mode 400 kHz I2C with wide margin against the sub-33 MHz open-drain limit. Tie EN HIGH during operation; pulling it LOW tri-states all I/O for hot-plug or power-down scenarios.
Recommended
Mixed-Voltage GPIO Interfacing
When a low-voltage microcontroller must drive or sense 5 V industrial sensors, optocoupler inputs, or legacy logic, the NVT2002DP,118 bridges the domains safely: the A side tolerates 1.0 V to 3.6 V references while the B side operates at 1.8 V to 5.5 V. Each channel passes signals in both directions with identical electrical characteristics, so a single TSSOP-8 device replaces discrete two-transistor shift circuits and their matching resistors, cutting board area and BOM variance. Push-pull GPIO translation requires pull-up resistors on each line, so engineers should size them against drive strength and edge-rate needs. The sub-33 MHz class bandwidth comfortably covers typical GPIO status, control, and interrupt lines running at kilohertz to low-megahertz rates in PLC I/O racks and instrumentation front ends.
Recommended
SMBus and PMBus Power-System Management
Server, telecom, and battery-management systems commonly run SMBus/PMBus management traffic at 3.3 V while power-supply modules, battery chargers, or hot-swap controllers expose 5 V management ports. The NVT2002DP,118 shifts this two-wire bus cleanly because SMBus, like I2C, is open-drain and bidirectional with clock stretching - the translator's direction-pin-free architecture handles it without host intervention. Both channels provide minimal output-to-output deviation, keeping SCL and SDA timing symmetric. The EN pin allows the management controller to isolate the bus when a PSU slot is unpowered, and low disabled-state supply current suits always-on standby rails. Verify resistor sizing against the SMBus 1 mA sink-current requirement, which constrains pull-up values on the 5 V side.
Recommended
Automotive Body Electronics and Gateways
Automotive body-control modules frequently mix a 3.3 V MCU domain with 5 V sensor and switch inputs, and the NVT2002 family is positioned for such translation duties in NXP's automotive ecosystem. The device bridges LIN transceiver digital enables, switch monitoring lines, and low-speed serial links between domains while eliminating latch-up risk from direct 5 V injection into 3.3 V pins. Its compact TSSOP-8 footprint suits dense gateway PCBs. For formal automotive qualification, engineers should confirm the exact temperature grade and AEC-Q100 status of the ordering code on NXP's product page, since qualification varies by grade suffix. The EN pin supports module sleep sequencing, tri-stating the bus so residual leakage through the translator does not discharge the battery during park-off states.
Recommended
UART and Low-Speed Serial Link Translation
UART TX/RX lines are point-to-point push-pull signals, and the NVT2002DP,118 can shift a 1.8 V or 3.3 V MCU UART to a 5 V device (legacy modems, GPS modules, industrial printers) using one channel per direction. Each side needs a pull-up resistor; because driven-LOW states sink current through the opposite side's pull-up, choose values that respect the driver sink capability. The architecture supports typical UART baud rates up to several megabaud comfortably within the part's bandwidth class, with the one-shot accelerator aiding rising edges. This application uses both channels for a full duplex link in one 8-pin package. For very high baud rates or long cables, evaluate a dedicated auto-direction push-pull translator instead, since RC-limited edges set the practical ceiling.
Recommended
1-Wire and Single-Channel Open-Drain Buses
Single-wire protocols such as 1-Wire, Touch Memory, and various propriety open-drain status buses benefit from the NVT2002's transparent bidirectional behavior: any device may drive the line at any time, and the translator passes contention-free. Using just one of its two channels, designers still gain the part's low line capacitance and edge acceleration, which matter on parasitically powered 1-Wire networks where the same line carries both power and data. The second channel can serve a companion interrupt line, keeping the design to one small package. Connect Vref(A) to the 1.8 V to 3.3 V host rail and Vref(B) to the 5 V field bus, pull both sides up per protocol requirements, and tie EN HIGH. Biased operation keeps the line near the A-side threshold for reliable detection.
Recommended
Recommended Products Summary
Engineering reference data for NVT2002DP,118 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | PCA9306DP,118 | GTL2002DP,118 | NVT2002GM,125 |
|---|---|---|---|---|
| Package | TSSOP-8 (DP) | TSSOP-8 - same | TSSOP-8 - same | TSSOP-8 - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Channels | 2 bidirectional | 2 bidirectional | 2 bidirectional | 2 bidirectional |
| A-Side Voltage Range | 1.0 V to 3.6 V | 1.0 V to 3.6 V | 1.2 V to 3.6 V | 1.0 V to 3.6 V |
| B-Side Voltage Range | 1.8 V to 5.5 V | 1.8 V to 5.5 V | 1.65 V to 5.5 V | 1.8 V to 5.5 V |
| Direction Pin Required | No | No | No | No |
| Family Generation | Current NVT generation | Established PCA9306 generation | Earlier GTL generation | Same NVT generation |
Key Differentiators
- Wider A-side low-voltage support (vs GTL2002DP,118)
- Newer-generation silicon with matched channels (vs PCA9306DP,118)
- Direction-pin-free bidirectionality (vs Dual-supply CMOS translators (TXS/TXB class))
- Trade-off: pull-up current in push-pull mode (vs Push-pull auto-direction translators)
Design Notes
Pull-up resistor selection dominates both speed and static power. Each line's pull-up on the B side carries bias current through the internal Vref(B)-to-Vref(A) network, so overly strong pull-ups (e.g., 1 kilo-ohm) waste milliamperes continuously, while overly weak ones (e.g., 100 kilo-ohm) produce unacceptably slow rising edges at high bus capacitance. Start with 4.7 kilo-ohm per line on I2C-class buses and verify rise-time against 0.8473*RC (30% to 70% threshold criterion) with your measured bus capacitance. Estimated: at 5 V and 4.7 kilo-ohm with both lines LOW half the time, static draw is roughly 1 mA total.
Place the NVT2002 close to the voltage-domain boundary and keep A-side traces short, since the A rail is often a sensitive low-voltage plane shared with an MCU. Decouple both Vref(A) and Vref(B) with 100 nF ceramic capacitors placed within a few millimeters of pins 1 and 8. Tie EN either hard to Vref(B) for always-on translation, or drive it from a GPIO/GPIO-with-pull-down so the bus defaults to tri-state during MCU reset and power sequencing - this prevents partial-voltage back-powering of the low-voltage domain through the translator.
Common mistake: assuming push-pull mode works without pull-ups. The NVT2002 is a pull-up-based architecture even in push-pull applications - omitting resistors leaves rising edges unpowered. Second pitfall: applying a reference outside the specified window, e.g., 5 V on Vref(A); the A side is limited to 3.6 V max and exceeding it risks damage. Third: connecting Vref(B) below 1.8 V stops reliable translation. Also confirm hot-plug behavior: devices on an unpowered domain will back-drive through their pull-ups - the EN pin is your isolation mechanism.
The internal one-shot edge accelerator only boosts the first rising edge after a falling edge; at very light loads this is invisible, but at heavy bus capacitance (>100 pF) verify no double-clocking occurs on I2C due to overshoot on the accelerated edge. Scope both sides during bring-up. For mixed 1.8 V/5 V systems, check the A-side input low threshold margin: the biased line sits near Vref(A) plus a threshold, so 1.0 V A-side operation is the most marginal corner in the specification.
Compliance Information
Compliance data was not present in the provided web search results. NXP ordering-code suffix ,118 typically denotes standard packing; verify RoHS/REACH status on the official NXP product page (nxp.com/part/NVT2002DP) before design-in.
