PCA9546AD,112 - 4-Ch I2C Switch with Reset | NXP
MPN: PCA9546AD,112 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2.15 | $2.15 |
| 10 | $1.93 | $19.30 |
| 100 | $1.68 | $168.00 |
| 500 | $1.45 | $725.00 |
| 1,000 | $1.28 | $1,280.00 |
PCA9546AD,112 Overview
An I2C multiplexer switch is an interface IC that lets a single I2C or SMBus master share one upstream SCL/SDA pair among several downstream bus segments. Within the interface IC hierarchy (bus switch -> I2C multiplexer -> I2C/SMBus interface IC), these devices resolve address conflicts, isolate capacitive loading, and allow voltage-level translation between mixed-voltage buses such as 1.8 V, 2.5 V, 3.3 V and 5 V rails.
Key features include 1-of-4 bidirectional translating switches, SMBus-standard-compatible I2C logic, three hardware address pins (A0-A2) that allow up to eight PCA9546A devices on one bus, channel selection in any combination via the programmable control register, and power-up with all channels deselected. The low Ron pass switches preserve signal integrity at standard and fast I2C speeds.
The architecture fans the upstream SCL/SDA pair out to four downstream SCx/SDx pairs using transmission-gate switches. The active-LOW RESET input lets the system recover from a hung bus segment by restoring the power-up default (all channels deselected) without a full power cycle, an important fault-recovery feature in electrically noisy environments.
Typical applications include server and telecom shelf management (SMBus fan and sensor muxing), LCD/LED display panel I2C fan-out, isolating multiple EEPROM or sensor clusters with clashing addresses, and level shifting between 3.3 V and 5 V I2C domains.
Design consideration: budget the roughly 30 ohm switch resistance plus bus capacitance in your rise-time calculations; heavily loaded downstream segments may need reduced pull-up values or bus buffers.
This page synthesizes distributor pricing context, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for PCA9546AD,112 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
PCA9546AD
✅ Drop-In✓ In Stock
$0.7 / Unit
View Datasheet →TCA9546AD
✅ Drop-In📋 Reference alternative (not in catalog)
PCA9545AD,112
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
PCA9546AD,112 Maximum Ratings & Electrical Characteristics
| Function | 4-channel bidirectional translating I2C-bus switch with reset |
| Interface | I2C, SMBus |
| Supply Voltage Range | 2.3 V to 5.5 V |
| Channels | 4 (1 upstream pair, 4 downstream SCx/SDx pairs) |
| On-State Resistance (Ron) Max | 30 ohm |
| Reset Input | Active-LOW RESET |
| Address Pins | 3 (A0, A1, A2) - up to 8 devices on one bus |
| Level Translation | 1.8 V, 2.5 V, 3.3 V and 5 V buses |
| Power-Up Default | All switch channels deselected |
| Package | 16-SOIC (0.154 in, 3.90 mm width) |
| Mounting Type | Surface Mount |
| Packaging | Tube |
| Lead Free Status | Lead free |
| RoHS Status | Compliant |
| Lifecycle Status | End of Life (per NXP product page; continued supply via Rochester Electronics) |
PCA9546AD,112 Pin Configuration
| Pin 1 | A0 — Address input 0 |
| Pin 2 | A1 — Address input 1 |
| Pin 3 | A2 — Address input 2 |
| Pin 4 | RESET — Active-LOW reset input; restores power-up state (all channels deselected) |
| Pin 5 | VSS — Ground |
| Pin 6 | SDA0 — Serial data, channel 0 |
| Pin 7 | SCL0 — Serial clock, channel 0 |
| Pin 8 | SDA1 — Serial data, channel 1 |
| Pin 9 | SCL1 — Serial clock, channel 1 |
| Pin 10 | SDA2 — Serial data, channel 2 |
| Pin 11 | SCL2 — Serial clock, channel 2 |
| Pin 12 | SDA3 — Serial data, channel 3 |
| Pin 13 | SCL3 — Serial clock, channel 3 |
| Pin 14 | VDD — Supply voltage, 2.3 V to 5.5 V |
| Pin 15 | SCL — Serial clock, upstream bus |
| Pin 16 | SDA — Serial data, upstream bus |
Typical Applications
PCA9546AD,112 is suitable for 6 applications: Server and Telecom Shelf Management, LCD and Display Panel I2C Fan-Out, Sensor Cluster Address Expansion, Industrial Control and PLC Modules, Automotive Body and Infotainment Control, Battery-Powered Portable Devices.
Server and Telecom Shelf Management
The PCA9546AD,112 fits SMBus-based shelf management where one BMC must poll dozens of fans, hot-swap controllers and temperature sensors that frequently share I2C addresses. Its four selectable channel pairs let the manager isolate one FRU segment at a time, preventing an address clash or a hung slave on one shelf segment from blocking the entire management bus. The 2.3 V to 5.5 V supply matches common 3.3 V management rails, and the 30 ohm maximum Ron preserves signal margins on shelf backplanes. Critically, the active-LOW RESET input allows the BMC to recover a segment locked up by a failed FRU without rebooting the shelf, a key availability feature in telecom and data-center platforms.
Recommended
LCD and Display Panel I2C Fan-Out
In monitors and TVs, a single graphics scaler or TCON with one I2C port often must program an EDID EEPROM, a backlight controller, and a panel timing device that share address space. The PCA9546AD,112 fans the upstream SCL/SDA pair out to four downstream pairs, letting the host address each device exclusively. Its pass-gate architecture adds essentially no propagation delay and supports level translation between 3.3 V host buses and 5 V peripheral buses within the 2.3 V to 5.5 V supply range. Power-up with all channels deselected prevents bus contention during system bring-up, and the 16-SOIC package fits the narrow board edge typical of panel assemblies.
Recommended
Sensor Cluster Address Expansion
Many popular I2C sensors (temperature, humidity, accelerometers) offer only one or two fixed address options, so four or more identical sensors on one bus create conflicts. The PCA9546AD,112 solves this by placing each sensor on its own downstream channel selected via the control register; up to eight PCA9546A devices can coexist using the A0-A2 address pins, supporting dozens of sensors from one controller. The low 30 ohm Ron keeps rise times acceptable with typical 4.7 kohm pull-ups, and 2.3 V operation matches modern low-voltage sensor rails. The RESET input gives firmware a recovery path if a sensor latches the bus, improving field reliability in IoT gateways.
Recommended
Industrial Control and PLC Modules
Industrial I/O and PLC modules accumulate EEPROMs, RTCs, ADCs and power monitors that exceed the I2C address space of a single segment. The PCA9546AD,112 partitions these devices onto four switchable bus segments chosen in any combination, so a host can read a bank of channels in one scan cycle. The 5.5 V maximum supply tolerates industrial 5 V logic, and the electrically noisy environment makes the active-LOW RESET input especially valuable: a supervisor can clear a corrupted control register after a transient. The wide 2.3 V to 5.5 V range and 30 ohm Ron class switching maintain signal integrity across the long traces typical of backplane-mounted I/O cards.
Recommended
Automotive Body and Infotainment Control
Automotive head units and body controllers use I2C to reach tuners, audio codecs, and ambient-light controllers spread across several boards. The PCA9546AD,112 lets one MCU multiplex four such segments and translate between a 3.3 V SoC bus and 5 V peripheral buses in one device. Because audio components can hang the bus when mis-addressed, the hardware RESET input enables deterministic recovery without power cycling the infotainment stack. The low Ron pass switches add minimal attenuation to the bidirectional SCL/SDA waveforms at 100 kHz and 400 kHz, and the 16-SOIC package supports the compact two-sided PCB constructions used in automotive entertainment modules (verify temperature grade for the specific application).
Recommended
Battery-Powered Portable Devices
Handheld instruments, medical monitors and portable test gear often combine a low-power MCU at 1.8 V or 2.5 V with legacy 3.3 V or 5 V peripherals. The PCA9546AD,112 operates down to 2.3 V, making it directly compatible with single-cell battery rails, while its translating switches bridge to higher-voltage peripheral buses. The passive pass-gate design consumes negligible static power compared with active buffer-based multiplexers, extending battery life. Four channels cover a typical peripheral set (fuel gauge, display EEPROM, touch controller, sensor), and the control-register approach means channel switching costs only two I2C bytes. The RESET pin allows a wake-cycle bus cleanup after deep-sleep states.
Recommended
Recommended Products Summary
Engineering reference data for PCA9546AD,112 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | PCA9546AD | TCA9546AD | PCA9545AD,112 |
|---|---|---|---|---|
| Package | 16-SOIC (3.90 mm width) | 16-SOIC (3.90 mm width) - same | 16-SOIC (3.90 mm width) - same | 16-SOIC (3.90 mm width) - same |
| Brand | NXP Semiconductors | Texas Instruments | Texas Instruments | NXP Semiconductors |
| Channels | 4 | 4 | 4 | 4 |
| Supply Voltage | 2.3 V to 5.5 V | 1.65 V to 5.5 V | 1.65 V to 5.5 V | 2.3 V to 5.5 V |
| Reset / Enable Pin | Active-LOW RESET | Active-LOW RESET | Active-LOW RESET | Active-HIGH ENABLE (no reset) |
| On-State Resistance | 30 ohm max | 30 ohm class | 30 ohm class | 30 ohm class |
| Lifecycle Status | EOL (Rochester supply) | Active | Active | Active (verify with NXP) |
| Level Translation | 1.8 V / 2.5 V / 3.3 V / 5 V | 1.65 V to 5.5 V domains | 1.65 V to 5.5 V domains | 1.8 V / 2.5 V / 3.3 V / 5 V |
Key Differentiators
- Hardware reset for bus fault recovery (vs PCA9545AD,112)
- Active second-source availability (vs PCA9546AD (TI))
- Wider low-voltage compatibility in TI equivalents (vs TCA9546AD)
Design Notes
Drive or pull up the RESET pin deliberately - never leave it floating. An undriven RESET can pick up noise and randomly clear the control register, deselecting all channels mid-transaction. Tie it through an RC network to VDD or drive it from a supervisor/GPIO. Also remember that pulling RESET low mid-cycle aborts the current I2C transaction and sets the control register to 00h (all channels off), so firmware must re-select the channel after any reset event.
Account for the switch series resistance in bus rise-time budgets. With a worst-case Ron around 30 ohm plus trace and trace-out capacitance on both sides, heavily loaded 400 kHz segments may violate the I2C rise-time specification with standard 4.7 kohm pull-ups. Estimated: for 200 pF total bus capacitance, a 3.3 V bus with 4.7 kohm pull-ups gives roughly 0.847*RC = 0.95 us rise time, well above the 300 ns fast-mode limit - reduce pull-ups to 1-2 kohm or add a bus buffer such as the TCA9517 on long segments.
Place a 0.1 uF ceramic decoupling capacitor within 2 mm of the VDD pin (pin 14) with a solid via to the ground plane. Keep the upstream SDA/SCL pair (pins 15/16) routed away from the RESET trace to avoid capacitive coupling that could glitch the reset during fast bus edges. Because the part is EOL at NXP, consider laying out the SOIC-16 footprint so it also accepts the TI PCA9546AD/TCA9546AD - all are pin-identical, giving a zero-rework second source.
Compliance Information
Lead-free status per distributor listing (digchip specifications). RoHS compliance per NXP product page. REACH, halogen-free and conflict-minerals status not stated in provided data.
