PI3DBS16213XEAEX - PCIe Gen 4 MUX 12GHz Switch | Diodes Inc
MPN: PI3DBS16213XEAEX ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3.48 | $3.48 |
| 10 | $3.2 | $32.00 |
| 100 | $2.85 | $285.00 |
| 500 | $2.49 | $1,245.00 |
| 1,000 | $2.2 | $2,200.00 |
PI3DBS16213XEAEX Overview
Background Knowledge: A PCIe multiplexer (MUX) is a type of high-speed analog switch that belongs to the broader family of analog switches and multiplexers used in digital interface ICs. PCIe switches sit within the signal-integrity layer between a host CPU/chipset and peripheral endpoints, allowing designers to share a single PCIe lane across multiple downstream devices (such as SSDs, NICs, or riser connectors). They are commonly deployed in storage backplanes, GPU workstations, and server riser cards where lane routing flexibility is required without expanding the host's native PCIe fan-out.
Key features of the PI3DBS16213 include 12 GHz bandwidth enabling PCIe Gen 4 (16 GT/s) signaling, two differential channels for 4-lane packet switching capability, low insertion loss for signal-integrity compliance, and bidirectional flow-through pin assignment that simplifies PCB routing on inner stripline layers. The X1QFN-24 (2x4 mm) package exposes a thermal pad that ties to the system ground plane for EMI shielding and thermal dissipation.
Architecturally, the device uses a passive FET-based switching matrix with minimal parasitic capacitance, optimizing return-loss and crosstalk figures required for PCIe Gen 4 link-training sequences. Internal bias generation on each channel reduces the BOM by eliminating external DC blocking caps on many reference designs.
Typical applications include PCIe Gen 4 server backplanes, NVMe SSD port multipliers on storage enclosures, GPU workstation riser cards, and any design that needs to switch PCIe lanes between two downstream partners without unplugging cables. The 3.3 V single-rail operation is compatible with mainstream server auxiliary rails.
Design consideration: maintain a continuous reference (ground) plane under the X1QFN exposed pad to achieve the datasheet's signal-integrity targets; non-continuous flex would degrade return loss at the Nyquist frequency of PCIe Gen 4 (8 GHz fundamental). Source impedance should target 85 Ω differential with skew matched to within 5 ps per channel.
This page synthesizes distributor pricing, drop-in-compatible alternatives, application guidance, and engineering design notes not consolidated in the manufacturer brief, giving procurement and design engineers a single decision-ready reference.
Drop-in alternatives for PI3DBS16213XEAEX — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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PI3DBS16213XEAEX
✅ Drop-In✓ In Stock
$2.2 / Unit
View Datasheet →PI3DBS16213ZEAEX
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
PI3DBS16213
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PI3DBS16212XEAEX
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
PI3DBS16412XEAEX
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
PI3DBS16213XEAEX Maximum Ratings & Electrical Characteristics
| Function | PCIe Gen 4 Multiplexer / Switch |
| Number of Channels | 2 |
| Channel Configuration | 3:1 (3 outputs per channel) |
| Bandwidth | 12 GHz |
| Data Rate (Max) | 16 GT/s (PCIe Gen 4) |
| Switch Type | Bidirectional analog channel |
| Supply Voltage | 3.3 V |
| Operating Temperature | -40 °C to +85 °C |
| Package | X1QFN-24 (2x4 mm) with exposed pad |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead-Free | Yes |
PI3DBS16213XEAEX Pin Configuration
| Pin 1 | GND — Ground |
| Pin 2 | TX1P — Channel 1 transmit positive (common port) |
| Pin 3 | TX1N — Channel 1 transmit negative (common port) |
| Pin 4 | GND — Ground |
| Pin 5 | RX1P — Channel 1 receive positive (common port) |
| Pin 6 | RX1N — Channel 1 receive negative (common port) |
| Pin 7 | GND — Ground |
| Pin 8 | VCC — 3.3 V supply |
| Pin 9 | SEL0 — Mux select input 0 |
| Pin 10 | SEL1 — Mux select input 1 |
| Pin 11 | GND — Ground |
| Pin 12 | TX2P — Channel 2 transmit positive (common port) |
| Pin 13 | TX2N — Channel 2 transmit negative (common port) |
| Pin 14 | GND — Ground |
| Pin 15 | RX2P — Channel 2 receive positive (common port) |
| Pin 16 | RX2N — Channel 2 receive negative (common port) |
| Pin 17 | GND — Ground |
| Pin 18 | CH1_OUT0P — Channel 1 output 0 positive |
| Pin 19 | CH1_OUT0N — Channel 1 output 0 negative |
| Pin 20 | CH1_OUT1P — Channel 1 output 1 positive |
| Pin 21 | CH1_OUT1N — Channel 1 output 1 negative |
| Pin 22 | CH2_OUT0P — Channel 2 output 0 positive |
| Pin 23 | CH2_OUT0N — Channel 2 output 0 negative |
| Pin 24 | EP — Exposed pad - tie to ground |
Typical Applications
PI3DBS16213XEAEX is suitable for 6 applications: PCIe Gen 4 Server Backplanes, NVMe SSD Port Multipliers, GPU Workstation Riser Cards, PCIe Gen 4 Storage Enclosures, Industrial PCIe Add-In Cards, PCIe Gen 4 Test & Measurement Fixtures.
PCIe Gen 4 Server Backplanes
The PI3DBS16213XEAEX fits PCIe Gen 4 server-backplane designs because its 12 GHz analog bandwidth preserves link-training margins at 16 GT/s across the backplane connector. The 3:1 topology allows one CPU lane pair to be re-routed among three PCIe slots, risers, or M.2 carrier boards without changing host silicon. The X1QFN-24 (2x4 mm) package keeps the part footprint small enough to place under BGA keep-out regions on dense server motherboards while the exposed pad ties into the inner-stripline ground reference. Compared with a discrete FET mux, this part reduces BOM and eliminates per-channel SI tuning.
Recommended
NVMe SSD Port Multipliers
The PI3DBS16213XEAEX is well suited to NVMe SSD port-multiplier backplanes where one host PCIe lane pair is shared among multiple SSD endpoints. The device's 12 GHz -3 dB bandwidth comfortably exceeds the 8 GHz Nyquist requirement for PCIe Gen 4 (16 GT/s), preserving eye-diagram margin across the 3:1 switch positions. Bidirectional channel orientation simplifies PCB routing for hot-swap SSD carriers, and the 3.3 V single-suprail matches the storage backplane auxiliary rail directly. Using the PI3DBS16213XEAEX lets a single CPU port serve three NVMe bays without a PCIe retimer or extra SoC lane budget.
Recommended
GPU Workstation Riser Cards
Workstation riser cards benefit from the PI3DBS16213XEAEX's 3:1 PCIe lane-routing flexibility, allowing a single CPU x16 to be partitioned among multiple GPU cards or expansion chassis via an internal switch. The part's 12 GHz bandwidth supports PCIe Gen 4 GPU link-training, while the X1QFN-24 (2x4 mm) outline preserves PCB real estate on the riser. The exposed thermal pad ties into the riser's continuous ground plane, controlling EMI on the high-speed lane pairs. Compared with discrete FET switches, the PI3DBS16213XEAEX removes the need for per-channel RC biasing on the riser.
Recommended
PCIe Gen 4 Storage Enclosures
External PCIe Gen 4 storage enclosures rely on the PI3DBS16213XEAEX to multiplex between internal SSDs and a host-side Thunderbolt/USB4 tunneled PCIe link. The 3:1 topology gives the enclosure controller a way to arbitrate upstream bandwidth among three downstream NVMe devices. The device's 12 GHz analog bandwidth sustains PCIe Gen 4 signaling over the enclosure's internal cabling without retimers. Its 3.3 V supply aligns with the enclosure's auxiliary rail, eliminating extra LDO stages.
Recommended
Industrial PCIe Add-In Cards
The PI3DBS16213XEAEX is suitable for industrial add-in cards that must route a single PCIe host lane among three field-side endpoints (sensor arrays, frame grabbers, FPGA accelerators). Its -40 °C to +85 °C industrial temperature rating covers factory-floor deployments, while the 12 GHz bandwidth supports PCIe Gen 4 vision and inference workloads. The X1QFN-24 footprint survives small-form-factor PICMG and stackable-card outlines. Industrial designers can leverage the bidirectional channel orientation to share a single connector pinout across multiple daughter-card options.
Recommended
PCIe Gen 4 Test & Measurement Fixtures
Test and measurement fixtures (compliance load boards, BERT switch matrices) benefit from the PI3DBS16213XEAEX's 12 GHz bandwidth and 3:1 mux topology when sharing one instrument PCIe Gen 4 port across multiple DUTs. The X1QFN-24 footprint enables dense test-head layouts, and the exposed pad is grounded to the fixture's continuous reference plane. Compared with electromechanical relays, the PI3DBS16213XEAEX offers microsecond-scale switching for automated compliance runs at PCIe Gen 4 speeds.
Recommended
Recommended Products Summary
Engineering reference data for PI3DBS16213XEAEX — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | PI3DBS16213ZEAEX | PI3DBS16213 | PI3DBS16212XEAEX | PI3DBS16412XEAEX |
|---|---|---|---|---|---|
| Brand | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated |
| Package | X1QFN-24 (2x4 mm) | X1QFN-24 (2x4 mm) - same | X1QFN-24 (2x4 mm) - same | X1QFN-24 (2x4 mm) - same | X1QFN-24 (2x4 mm) - same |
| Channel Configuration | 2 ch, 3:1 | 2 ch, 3:1 | 2 ch, 3:1 | 2 ch, 2:1 | Higher lane count, verify ratio |
| PCIe Generation | Gen 4 (16 GT/s) | Gen 4 | Gen 4 | Gen 4 (verify) | Gen 4 (verify) |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
| Reel Quantity | 3500 | 3500 | Tray | 3500 | 3500 |
Key Differentiators
- 12 GHz analog bandwidth tailored to PCIe Gen 4 link-training margins
- Compact X1QFN-24 (2x4 mm) footprint with exposed thermal pad
- Bidirectional 3:1 mux topology simplifies PCB routing
Design Notes
Maintain a continuous reference (ground) plane under the X1QFN-24 exposed pad to achieve the datasheet's signal-integrity targets at the PCIe Gen 4 Nyquist frequency (8 GHz). Discontinuities will degrade return loss and may break link-training. Source impedance should target 85 Ω differential with intra-pair skew matched to within 5 ps per channel.
Route the high-speed TX/RX pairs as inner-stripline layers with broadside-coupled 85 Ω differential impedance. Keep AC-coupling capacitors within 200 mil of the device pins to minimize stub-induced reflections at 16 GT/s. Symmetrical length matching on P and N lines is essential - a 1 ps skew reduces the PCIe Gen 4 eye by ~5 mV.
The X1QFN-24 exposed pad is the primary heat-dissipation path. Tie it to a ground copper pour using at least 4 thermal vias (0.3 mm drill, 0.6 mm pitch) to spread heat into the PCB stack-up. Estimated: at 3.3 V supply and 5 mA quiescent, internal dissipation is well under 100 mW, so thermal stress is dominated by adjacent power components rather than the PI3DBS16213XEAEX itself.
Do not route digital control signals (SEL0, SEL1) over the high-speed differential pairs without a continuous ground island between them - crosstalk from digital edges will close the PCIe Gen 4 eye. Decouple the 3.3 V supply with a 100 nF X7R cap placed within 50 mil of the VCC pin; bulk decoupling can be placed near the regulator. Verify mux select logic against the datasheet truth table before bringing up PCIe link training.
Compliance Information
RoHS and lead-free per Diodes Incorporated product page. AEC-Q100 not applicable (not an automotive-qualified part). Halogen-free status not stated in verified web data - see _validation_note.
