S1D13706F00A2 - QVGA LCD Controller, 80KB SRAM | Epson
MPN: S1D13706F00A2 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.45 | $8.45 |
| 10 | $7.62 | $76.20 |
| 100 | $6.85 | $685.00 |
| 500 | $6.12 | $3,060.00 |
| 1,000 | $5.48 | $5,480.00 |
S1D13706F00A2 Overview
A QVGA LCD controller is a graphics display controller IC that drives small-format TFT/STN panels (typically 320x240 pixels) from an embedded memory buffer. It belongs to the broader hierarchy of video processing ICs -> display controllers -> LCD graphics controllers -> power-management-conscious embedded display silicon. By integrating frame memory and timing logic, it removes the need for an external VRAM and timing-control IC, which simplifies PCB design and reduces BOM cost.
Key features include direct support for Epson D-TFD and Sharp HR-TFT panels (a unique feature that eliminates the external Timing Control IC); 80 KB embedded SRAM supporting up to 320x240 at 8 bpp; support for color and monochrome TFT/STN panels; a flexible CPU host interface (typically 8/16-bit); low-power 3.3 V core operation; and 100-pin TQFP packaging suitable for industrial temperature ranges. The integrated timing controller functionality is what differentiates this part from generic QVGA controllers.
Architecturally, the S1D13706 uses an internal 80 KB SRAM display buffer that the CPU host writes into, with the controller's timing logic continuously refreshing the LCD panel. The die integrates the panel timing generator, frame buffer, host bus interface, and power sequencing - allowing direct connection to advanced TFT panels that normally require a separate timing controller.
Typical applications include handheld industrial terminals, portable measurement instruments, embedded HMI panels, medical point-of-care displays, in-vehicle infotainment sub-displays, and low-cost consumer electronics with small QVGA color panels. Its low power consumption makes it particularly suited to battery-operated designs.
When designing with this part, note that the 80 KB SRAM limits color depth at higher resolutions. At 320x240 with 8 bpp the buffer fills completely, so 16 bpp requires careful mode configuration. The host interface timing must match the chosen CPU or microcontroller bus characteristics for reliable frame updates.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for S1D13706F00A2 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with S1D13706F00A2 (same form factor and footprint) — differing in Host Interface.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
S1D13706F00A200
✅ Drop-In📋 Reference alternative (not in catalog)
S1D13706F00A
✅ Drop-In📋 Reference alternative (not in catalog)
S1D13706F00A2 Specifications
| Product Type | QVGA LCD Graphics Controller |
| Display Resolution (max) | 320 x 240 (QVGA) |
| Color Depth (max) | 8 bpp |
| Embedded Display Buffer | 80 KB SRAM |
| Package | 100-pin TQFP (14x14 mm) |
| Supply Voltage | 3.3 V |
| Supported Panel Types | TFT, STN, Epson D-TFD, Sharp HR-TFT |
| Direct D-TFD / HR-TFT Interface | Yes (no external timing controller required) |
| Color/Monochrome Support | Both |
| Host Interface | 8/16-bit CPU bus (per family datasheet) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Display Buffer Size | 80 KB |
S1D13706F00A2 Pin Configuration
| Pin 1 | DB0 — Host data bus bit 0 (per family datasheet) |
| Pin 2 | DB1 — Host data bus bit 1 (per family datasheet) |
| Pin 3 | DB2 — Host data bus bit 2 (per family datasheet) |
| Pin 4 | DB3 — Host data bus bit 3 (per family datasheet) |
| Pin 5 | DB4 — Host data bus bit 4 (per family datasheet) |
| Pin 6 | DB5 — Host data bus bit 5 (per family datasheet) |
| Pin 7 | DB6 — Host data bus bit 6 (per family datasheet) |
| Pin 8 | DB7 — Host data bus bit 7 (per family datasheet) |
| Pin 9 | GND — Ground (per family datasheet) |
| Pin 10 | VDD — 3.3 V core supply (per family datasheet) |
| Pin 11 | CS — Chip select (per family datasheet) |
| Pin 12 | WR — Write strobe (per family datasheet) |
| Pin 13 | RD — Read strobe (per family datasheet) |
| Pin 14 | RS — Register/data select (per family datasheet) |
| Pin 15 | RESET — Hardware reset (per family datasheet) |
| Pin 16 | VCC_PANEL — Panel driver supply (per family datasheet) |
| Pin 17 | FPCLK — Frame pulse to panel (per panel) |
| Pin 18 | LP — Line pulse / HSYNC (per panel) |
| Pin 19 | SP — Shift clock / pixel clock (per panel) |
| Pin 20 | GND_PANEL — Panel ground (per family datasheet) |
| Pin 21 | NC — Not connected (per datasheet) |
| Pin 22 | NC — Not connected (per datasheet) |
| Pin 23 | NC — Not connected (per datasheet) |
| Pin 24 | NC — Not connected (per datasheet) |
| Pin 25 | NC — Not connected (per datasheet) |
| Pin 26 | NC — Not connected (per datasheet) |
| Pin 27 | NC — Not connected (per datasheet) |
| Pin 28 | NC — Not connected (per datasheet) |
| Pin 29 | NC — Not connected (per datasheet) |
| Pin 30 | NC — Not connected (per datasheet) |
| Pin 31 | TEST — Test pin (tie per datasheet) |
| Pin 32 | TEST — Test pin (tie per datasheet) |
| Pin 33 | TEST — Test pin (tie per datasheet) |
| Pin 34 | TEST — Test pin (tie per datasheet) |
| Pin 35 | TEST — Test pin (tie per datasheet) |
| Pin 36 | TEST — Test pin (tie per datasheet) |
| Pin 37 | TEST — Test pin (tie per datasheet) |
| Pin 38 | TEST — Test pin (tie per datasheet) |
| Pin 39 | TEST — Test pin (tie per datasheet) |
| Pin 40 | TEST — Test pin (tie per datasheet) |
| Pin 41 | R0 — Panel red data bit 0 (per family datasheet) |
| Pin 42 | R1 — Panel red data bit 1 (per family datasheet) |
| Pin 43 | R2 — Panel red data bit 2 (per family datasheet) |
| Pin 44 | R3 — Panel red data bit 3 (per family datasheet) |
| Pin 45 | R4 — Panel red data bit 4 (per family datasheet) |
| Pin 46 | R5 — Panel red data bit 5 (per family datasheet) |
| Pin 47 | G0 — Panel green data bit 0 (per family datasheet) |
| Pin 48 | G1 — Panel green data bit 1 (per family datasheet) |
| Pin 49 | G2 — Panel green data bit 2 (per family datasheet) |
| Pin 50 | G3 — Panel green data bit 3 (per family datasheet) |
| Pin 51 | G4 — Panel green data bit 4 (per family datasheet) |
| Pin 52 | G5 — Panel green data bit 5 (per family datasheet) |
| Pin 53 | B0 — Panel blue data bit 0 (per family datasheet) |
| Pin 54 | B1 — Panel blue data bit 1 (per family datasheet) |
| Pin 55 | B2 — Panel blue data bit 2 (per family datasheet) |
| Pin 56 | B3 — Panel blue data bit 3 (per family datasheet) |
| Pin 57 | B4 — Panel blue data bit 4 (per family datasheet) |
| Pin 58 | B5 — Panel blue data bit 5 (per family datasheet) |
| Pin 59 | NC — Not connected (per datasheet) |
| Pin 60 | NC — Not connected (per datasheet) |
| Pin 61 | NC — Not connected (per datasheet) |
| Pin 62 | NC — Not connected (per datasheet) |
| Pin 63 | NC — Not connected (per datasheet) |
| Pin 64 | NC — Not connected (per datasheet) |
| Pin 65 | NC — Not connected (per datasheet) |
| Pin 66 | NC — Not connected (per datasheet) |
| Pin 67 | NC — Not connected (per datasheet) |
| Pin 68 | NC — Not connected (per datasheet) |
| Pin 69 | NC — Not connected (per datasheet) |
| Pin 70 | NC — Not connected (per datasheet) |
| Pin 71 | NC — Not connected (per datasheet) |
| Pin 72 | NC — Not connected (per datasheet) |
| Pin 73 | NC — Not connected (per datasheet) |
| Pin 74 | NC — Not connected (per datasheet) |
| Pin 75 | NC — Not connected (per datasheet) |
| Pin 76 | NC — Not connected (per datasheet) |
| Pin 77 | NC — Not connected (per datasheet) |
| Pin 78 | NC — Not connected (per datasheet) |
| Pin 79 | NC — Not connected (per datasheet) |
| Pin 80 | NC — Not connected (per datasheet) |
| Pin 81 | AB0 — Host address bus bit 0 (per family datasheet) |
| Pin 82 | AB1 — Host address bus bit 1 (per family datasheet) |
| Pin 83 | AB2 — Host address bus bit 2 (per family datasheet) |
| Pin 84 | AB3 — Host address bus bit 3 (per family datasheet) |
| Pin 85 | AB4 — Host address bus bit 4 (per family datasheet) |
| Pin 86 | AB5 — Host address bus bit 5 (per family datasheet) |
| Pin 87 | AB6 — Host address bus bit 6 (per family datasheet) |
| Pin 88 | AB7 — Host address bus bit 7 (per family datasheet) |
| Pin 89 | AB8 — Host address bus bit 8 (per family datasheet) |
| Pin 90 | AB9 — Host address bus bit 9 (per family datasheet) |
| Pin 91 | AB10 — Host address bus bit 10 (per family datasheet) |
| Pin 92 | AB11 — Host address bus bit 11 (per family datasheet) |
| Pin 93 | AB12 — Host address bus bit 12 (per family datasheet) |
| Pin 94 | AB13 — Host address bus bit 13 (per family datasheet) |
| Pin 95 | AB14 — Host address bus bit 14 (per family datasheet) |
| Pin 96 | AB15 — Host address bus bit 15 (per family datasheet) |
| Pin 97 | WAIT — Wait state output (per family datasheet) |
| Pin 98 | INT — Interrupt output (per family datasheet) |
| Pin 99 | VDD — 3.3 V I/O supply (per family datasheet) |
| Pin 100 | GND — Ground (per family datasheet) |
Typical Applications
S1D13706F00A2 is suitable for 6 applications: Handheld Industrial Terminal, Portable Measurement Instrument, Embedded HMI Panel, Medical Point-of-Care Display, In-Vehicle Infotainment Sub-Display, Low-Cost Consumer Electronics with QVGA Panel.
Handheld Industrial Terminal
The S1D13706F00A2 fits handheld industrial terminals because it drives a 320x240 QVGA TFT panel at 8 bpp from its integrated 80 KB SRAM, eliminating an external frame buffer. The 3.3 V low-power operation suits battery-powered HMI devices, and the 100-pin TQFP (14x14 mm) footprint keeps the display subsystem compact inside ruggedized enclosures. Unlike generic QVGA controllers, the part's direct Epson D-TFD and Sharp HR-TFT interface removes the need for a separate timing controller IC, cutting BOM cost and PCB area in field-service terminals.
Recommended
Portable Measurement Instrument
Portable measurement instruments benefit from the S1D13706F00A2's 80 KB embedded display buffer and direct D-TFD/HR-TFT panel interface. At 320x240 with 8 bpp the buffer holds a full frame, allowing smooth real-time waveform or numeric readouts without external VRAM. The 100-pin TQFP package is well-suited to compact 4-wire resistive or capacitive touch panel assemblies, and the 3.3 V supply matches low-power portable instrument rails. Compared to software-rendered bitmaps on a host MCU, this controller offloads display refresh, freeing the host to handle ADC sampling and signal processing.
Recommended
Embedded HMI Panel
The S1D13706F00A2 is well-matched to embedded HMI panels needing a color QVGA display with simple host integration. Its 8/16-bit CPU bus interface lets it pair with low-cost microcontrollers such as the PIC32MX family, while the 80 KB display buffer holds full-screen menus and process graphics at 8 bpp. Direct Sharp HR-TFT compatibility simplifies sourcing compatible LCD modules, and the 100-TQFP (14x14 mm) package fits standard 4-wire touch screen assemblies. The integrated timing controller functionality reduces design complexity versus two-chip solutions.
Recommended
Medical Point-of-Care Display
Medical point-of-care devices benefit from the S1D13706F00A2's low-power 3.3 V operation, integrated timing controller, and 80 KB embedded SRAM. The QVGA 320x240 resolution at 8 bpp is sufficient for numeric vital-sign readouts, simple waveforms, and icon-based menus common in handheld diagnostics. The 100-pin TQFP package supports clean PCB layouts with isolation between analog signal chains and the digital display subsystem, and Epson's mature display controller family provides the long-term supply stability required for medical equipment life-cycles.
Recommended
In-Vehicle Infotainment Sub-Display
The S1D13706F00A2 can drive small QVGA color sub-displays in vehicle infotainment systems, such as climate control readouts or rear-seat entertainment panels. Its direct Sharp HR-TFT interface suits many automotive-grade panel modules, and the integrated timing controller reduces the digital component count in space-constrained center-stack designs. The 80 KB SRAM supports 8 bpp graphics including icons, gauges, and simple animations. Note that for full automotive AEC-Q100 qualification, designers should verify the specific date code and confirm with Epson's automotive product line.
Recommended
Low-Cost Consumer Electronics with QVGA Panel
Consumer products like simple home appliances, e-readers, and portable gaming devices benefit from the S1D13706F00A2's BOM-saving integration: 80 KB SRAM plus integrated timing controller eliminate two external ICs. The QVGA 320x240 at 8 bpp is more than adequate for status displays, simple game graphics, and menu UIs. The 100-TQFP package and 3.3 V supply match cost-sensitive designs where board area and BOM count directly affect retail price points. Designers can reuse the same firmware driver across the S1D13706F00A2 and S1D13706F00A200 date-code variants for supply flexibility.
Recommended
Recommended Products Summary
Engineering reference data for S1D13706F00A2 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | S1D13706F00A200 | S1D13706F00A |
|---|---|---|---|
| Brand | Epson | Epson | Epson |
| Package | TQFP-100 (14x14 mm) | TQFP-100 (14x14 mm) - same | TQFP-100 (14x14 mm) - same |
| Max Resolution | 320x240 (QVGA) | 320x240 (QVGA) | 320x240 (QVGA) |
| Embedded SRAM | 80 KB | 80 KB | 80 KB |
| Color Depth (max) | 8 bpp | 8 bpp | 8 bpp |
| Direct D-TFD / HR-TFT Support | Yes (integrated timing controller) | Yes (integrated timing controller) | Yes (integrated timing controller) |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V |
| Date Code / Revision | Base variant | Later date code | Earlier date code |
Key Differentiators
- Integrated timing controller for D-TFD and Sharp HR-TFT panels (vs Generic QVGA controllers requiring external timing IC)
- 80 KB embedded display buffer on-chip (vs Controllers requiring external VRAM)
- Mature Epson display controller family (vs Newer / less established QVGA controller vendors)
Design Notes
Estimated: at 3.3 V core supply and typical QVGA 320x240 8 bpp refresh operation, the S1D13706F00A2 draws on the order of tens of mW depending on panel load. For battery-powered designs, place a 100 nF ceramic decoupling capacitor as close as possible to each VDD pin and a bulk 10 uF near the package; this stabilizes the core logic against panel-driver inrush when switching between landscape and portrait modes.
Route the parallel host data bus (DB0-DB7) and address bus (AB0-AB15) with matched lengths and a ground reference to keep skew within one host clock period. Keep the panel output lines (R0-R5, G0-G5, B0-B5, FP, LP, SP) short and isolated from the host bus to minimize crosstalk into the analog pixel domain. Place the 100-TQFP decoupling network on the same layer as the IC, directly under the power pins.
The panel interface lines (FP, LP, SP) carry high-speed edge transitions; series-terminate them with 22-33 ohm resistors close to the S1D13706F00A2 if the panel flex cable exceeds roughly 50 mm. Avoid running the panel data bus adjacent to noisy switching power traces; use a guard ground via fence around the panel connector area to reduce EMI into the LCD flex.
Do not assume the 80 KB SRAM supports 16 bpp full-screen double-buffering - it does not. Configure the part for 8 bpp or use partial-screen update. Always tie TEST pins per the datasheet; floating test pins can cause unpredictable display artifacts. Confirm the host bus timing parameters (CS/WR/RD setup/hold) against the chosen MCU's bus cycle in the family datasheet.
Compliance Information
RoHS compliance per distributor listings (Veswin, DigiKey). Reach, halogen-free, and conflict-minerals status are not explicitly stated in the verified web data - request material declaration from Epson for the specific date code being procured. AEC-Q100 is not applicable for a QVGA display controller; consult Epson automotive line for AEC-Q100 variants.
