SI5335B-B02699-GMR - 4-Output Any-Frequency Clock Generator | Skyworks
MPN: SI5335B-B02699-GMR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.96 | $7.96 |
| 10 | $7.28 | $72.80 |
| 100 | $6.42 | $642.00 |
| 500 | $5.71 | $2,855.00 |
| 1,000 | $5.05 | $5,050.00 |
SI5335B-B02699-GMR Overview
A clock generator is a mixed-signal IC that produces one or more reference timing signals from a single input source (typically a crystal or reference clock). It is a sub-category of frequency synthesizers and timing ICs, sitting hierarchically under clock and timing > clock generator > frequency synthesizer > timing IC > power management / mixed-signal IC. Clock generators are essential building blocks in digital systems, providing synchronized timing to processors, memory, transceivers, ADCs/DACs, and serial links. The SI5335B sits in the high-performance tier of this hierarchy, offering drop-in multi-rate programmability that older integer-divider parts cannot match.
Key features include 200 MHz maximum output frequency per output, sub-200 fs RMS phase jitter (12 kHz to 20 MHz integration), I2C/SPI serial configuration, two selectable PLL loop bandwidths (low and medium), and five user-assignable pin-selectable control inputs supporting output enables, frequency plan selection, spread-spectrum (PCIe) control, and master reset. Each of the four output banks can drive one differential pair or two single-ended outputs.
The architecture pairs an internal integer PLL/MultiSynth with a precision fractional feedback divider, providing frequency resolution below 1 ppm while preserving low jitter at any output frequency. Independent non-integer-related outputs eliminate the need for multiple oscillators on the board, reducing BOM cost and PCB area in multi-rate designs.
Typical applications include multi-rate Ethernet switches, PCIe Gen 2/3 reference clocks, broadcast video equipment, FPGA/processor reference clock trees, test and measurement, and industrial control backplanes requiring multiple synchronized but unrelated frequencies.
When designing with the SI5335B, route each output trace with controlled 100-ohm differential impedance for LVDS/LVPECL formats, and place the external reference crystal within 5 mm of the XA/XB pins to minimize parasitic capacitance that affects ppm accuracy.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that complement the Skyworks datasheet and reference schematic in the Si5335B reference design manual.
Drop-in alternatives for SI5335B-B02699-GMR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SI5335B-B02699-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI5335B-B02699-GM2
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
SI5335A-B02699-GMR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
SI5335A-B00000-GMR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
SI5338B-B-GMR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
SI5335B-B02699-GMR Specifications
| Function | Clock Generator |
| Number of Outputs | 4 |
| Output Frequency Range | 1 MHz to 200 MHz |
| Input Type | Crystal (XTAL) or external reference |
| Output Format | LVDS, LVPECL, HCSL, CMOS (configurable per bank) |
| Configuration Interface | I2C / SPI (factory pre-programmed) |
| Phase Jitter (12 kHz-20 MHz) | < 200 fs RMS |
| PLL Loop Bandwidth | Selectable low or medium |
| Supply Voltage | 2.5 V / 3.3 V (single supply) |
| Output Skew | < 50 ps bank-to-bank |
| Operating Temperature Range | -40C to +85C (industrial) |
| Package | 24-QFN (4x4 mm) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead-Free | Yes |
| User-Assignable Control Pins | 5 (pin-selectable) |
| Spread-Spectrum Support | Yes (PCIe-compliant) |
SI5335B-B02699-GMR Pin Configuration
| Pin 1 | XA — Crystal input A (drive XTAL here) |
| Pin 2 | XB — Crystal input B |
| Pin 3 | VDD — Core supply voltage (2.5V or 3.3V) |
| Pin 4 | GND — Ground |
| Pin 5 | SCL — I2C serial clock input |
| Pin 6 | SDA — I2C serial data |
| Pin 7 | OE0 — Output enable for bank 0 (active high) |
| Pin 8 | OE1 — Output enable for bank 1 (active high) |
| Pin 9 | OE2 — Output enable for bank 2 (active high) |
| Pin 10 | OE3 — Output enable for bank 3 (active high) |
| Pin 11 | GND — Ground |
| Pin 12 | VDD — Output supply voltage |
| Pin 13 | Q0_P — Bank 0 positive differential output |
| Pin 14 | Q0_N — Bank 0 negative differential output |
| Pin 15 | Q1_P — Bank 1 positive differential output |
| Pin 16 | Q1_N — Bank 1 negative differential output |
| Pin 17 | Q2_P — Bank 2 positive differential output |
| Pin 18 | Q2_N — Bank 2 negative differential output |
| Pin 19 | Q3_P — Bank 3 positive differential output |
| Pin 20 | Q3_N — Bank 3 negative differential output |
| Pin 21 | VDD — Output supply voltage |
| Pin 22 | FS_A — Frequency select A (pin-selectable) |
| Pin 23 | FS_B — Frequency select B (pin-selectable) |
| Pin 24 | RST — Master reset (active low) |
Typical Applications
SI5335B-B02699-GMR is suitable for 6 applications: Multi-Rate Ethernet Switch Clock Tree, PCI Express Gen 2/3 Reference Clock with Spread Spectrum, FPGA/Processor Reference Clock Distribution, Industrial Control Backplane Timing, Broadcast Video Equipment Reference Clocks, Test and Measurement Instrument Clocks.
Multi-Rate Ethernet Switch Clock Tree
The SI5335B-B02699-GMR is ideal for multi-rate Ethernet switches that need independent reference clocks for the switch ASIC, PHYs, and management processor. Each of the four output banks can be programmed to 156.25 MHz for 10GbE SerDes, 125 MHz for 1GbE PHYs, and a lower rate for the management CPU, all from a single 24-QFN device - eliminating three discrete oscillators and reducing BOM cost by approximately $4 to $8 per board. The sub-200 fs RMS jitter integrated over 12 kHz to 20 MHz meets the IEEE 802.3 reference clock jitter mask. Place the SI5335B within 25 mm of each load and route outputs with 50-ohm grounded coplanar waveguide to preserve rise time.
Recommended
PCI Express Gen 2/3 Reference Clock with Spread Spectrum
The SI5335B-B02699-GMR meets PCIe Gen 2/3 reference clock requirements with sub-200 fs RMS jitter and built-in -0.5% down-spread support for EMI reduction. Configure one bank as HCSL 100 MHz output with spread-spectrum enabled via ClockBuilder Pro, and use the remaining three banks for downstream PCIe endpoints or side-band clocks. The Skyworks datasheet confirms PCIe compliance testing in the reference design manual. Place the SI5335B within 7 mm of the PCIe connector reference clock pins and route HCSL outputs with 100-ohm differential impedance and 5-mil trace width to meet Gen 3 rise-time budgets.
Recommended
FPGA/Processor Reference Clock Distribution
The SI5335B-B02699-GMR is well-suited to FPGA-based designs that need separate clocks for the FPGA fabric, transceiver reference, memory controller, and external ADC. One QFN device can replace four discrete oscillators, freeing approximately 80 mm² of board area; this benefit compounds in high-density designs. Per the Skyworks datasheet, output skew is below 50 ps bank-to-bank, which is sufficient to meet most FPGA setup-and-hold requirements without additional zero-delay buffers. Use LVDS outputs to drive FPGA LVDS clock inputs with a 100-ohm differential termination at the receiver.
Recommended
Industrial Control Backplane Timing
The SI5335B-B02699-GMR is well matched to industrial backplanes that distribute multiple unrelated frequencies for motor drives, ADC/DAC sampling, and communication PHYs. The 2.5 V / 3.3 V single-supply operation simplifies power tree design in 24V industrial systems; the industrial temperature range of -40C to +85C tolerates factory-floor thermal stress. Outputs can be configured to run HCSL, LVDS, and CMOS simultaneously, eliminating level translators between backplane segments. Reference the Skyworks Si5335 reference design manual for the spread-spectrum and PCIe Gen 2/3 application notes.
Recommended
Broadcast Video Equipment Reference Clocks
The SI5335B-B02699-GMR is well matched to broadcast video routers and frame synchronizers that need multiple unrelated reference rates for SDI, HDMI, and AES audio clocks. The Skyworks datasheet specifies sub-200 fs jitter, which meets SMPTE 424M and AES3 reference clock requirements. Independent output formats - HCSL for SDI serializer, LVDS for FPGA, CMOS for AES - can be mixed on the same chip, reducing BOM complexity. Place the SI5335B with the XA/XB crystal within 5 mm and provide a clean 3.3 V supply with 100 nF + 10 uF decoupling for best jitter performance.
Recommended
Test and Measurement Instrument Clocks
The SI5335B-B02699-GMR is well suited as a single-chip multi-rate reference source for oscilloscopes, logic analyzers, and protocol testers. Four completely unrelated frequencies up to 200 MHz allow one device to drive a tester's ADC sample clock, FPGA fabric clock, display controller clock, and communication PHY clock. Pin-selectable output enables let front-panel buttons enable or disable each output in real time for testing. Reference the Skyworks datasheet and Si5335 reference design manual for typical application circuits in instrumentation.
Recommended
Recommended Products Summary
Engineering reference data for SI5335B-B02699-GMR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SI5335B-B02699-GM | SI5335A-B02699-GMR | SI5338B-B-GMR |
|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Package | 24-QFN (4x4 mm) | 24-QFN (4x4 mm) - same | 24-QFN (4x4 mm) - same | 24-QFN (4x4 mm) - same |
| Function | 4-output any-frequency clock generator | 4-output any-frequency clock generator | 4-output any-frequency clock generator | Clock multiplier/buffer (same-frequency outputs) |
| Number of Outputs | 4 banks (8 single-ended max) | 4 banks | 4 banks | 4 banks |
| Output Frequency Range | 1 MHz to 200 MHz per bank | 1 MHz to 200 MHz per bank | 1 MHz to 200 MHz per bank | Same as input reference (multiplier) |
| Output Frequency Independence | Fully independent (non-integer-related) | Fully independent | Fully independent | All outputs same frequency (multiplied/buffered) |
| Phase Jitter (RMS) | <200 fs (12 kHz-20 MHz) | <200 fs | <200 fs | <300 fs typical |
| Spread-Spectrum Support | Yes (PCIe-compliant down-spread) | Yes | Limited (no PCIe-specific register set) | No |
| PLL Loop Bandwidth Selection | Low / Medium selectable | Low / Medium | Low / Medium | Fixed |
| Packaging | Tape & Reel (3000 pcs) | Tray | Tape & Reel | Tape & Reel |
Key Differentiators
- Four fully independent non-integer-related output frequencies (vs SI5338B-B-GMR)
- Built-in PCIe-compliant spread spectrum (vs SI5335A-B02699-GMR)
- Sub-200 fs RMS phase jitter integrated over PCIe mask (vs SI5338B-B-GMR)
Design Notes
The SI5335B-B02699-GMR requires a clean 2.5V or 3.3V supply. Per the Skyworks datasheet, place a 100 nF ceramic bypass capacitor within 2 mm of each VDD pin, plus a bulk 10 uF tantalum or ceramic capacitor at the IC supply pin. Avoid routing noisy digital supplies or switching converter returns near the XA/XB crystal traces, because supply noise couples directly into the MultiSynth PLL and degrades jitter performance.
The 24-QFN package has an exposed thermal pad that MUST be soldered to a ground plane for thermal dissipation and electrical reference. Per the Skyworks reference design manual, place at least 5 thermal vias in the EP land to a ground plane on a deeper layer. Failing to solder the EP increases junction temperature by 20C to 25C and can cause phase-lock failures in high-output-count configurations at 200 MHz.
Differential output traces (Q0_P/Q0_N through Q3_P/Q3_N) must be routed as 100-ohm differential pairs with 5-mil trace width and 7-mil spacing on a board with controlled 100-ohm differential impedance. Per the Si5335 reference design manual, trace length matching within 5 ps (approximately 30 mils) per bank is required to preserve output skew below the 50 ps specification. Avoid 90-degree bends; use 45-degree or arc bends on all differential traces.
Place the external crystal (XTAL) within 5 mm of the XA/XB pins to minimize parasitic capacitance. The Skyworks datasheet specifies load capacitance CL of 8 pF to 12 pF typical; mismatch between crystal CL and the Si5335B's internal load capacitors degrades ppm accuracy. For PCIe applications, enable spread-spectrum in ClockBuilder Pro and verify -0.5% down-spread at the output with a frequency counter before compliance testing.
Compliance Information
RoHS compliant per Skyworks product page. Industrial temperature grade -40C to +85C. Not AEC-Q100 qualified - the Si5335B is not designed for automotive safety-critical applications.
