SI5335B-B03900-GMR - 4-Output Any-Frequency Clock Generator | Skyworks
MPN: SI5335B-B03900-GMR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.85 | $5.85 |
| 10 | $5.21 | $52.10 |
| 100 | $4.45 | $445.00 |
| 500 | $3.92 | $1,960.00 |
| 1,000 | $3.48 | $3,480.00 |
SI5335B-B03900-GMR Overview
A clock generator is a timing IC that produces one or more precision reference frequencies from a single input reference, replacing multiple crystal oscillators and reducing BOM cost. The SI5335 family falls within the broader hierarchy of clock generators -> frequency synthesizers -> PLL-based timing ICs -> clock & timing semiconductors. Unlike fixed-frequency XOs, the SI5335B can be factory- or web-configured to deliver any combination of output frequencies, output formats (LVDS, LVPECL, HCSL, CMOS), and drive strengths, making it a universal replacement for up to four separate oscillators.
Key features include sub-200 ps peak-to-peak output-to-output skew, integrated 50 ohm output termination options, per-bank output enable/disable control, and I2C/SPI host interface for in-system reconfiguration. The internal MultiSynth architecture eliminates the need for external loop filter components and supports glitchless output frequency changes. The 1.8 V core with separate VDDO banks for each output allows mixed-voltage designs where one bank drives 1.8 V LVDS logic while another drives 3.3 V LVPECL PHYs without level translators.
Technical depth: the MultiSynth fractional-N architecture permits arbitrary frequency synthesis with no integer-multiple relationship constraint between outputs. Each MultiSynth block contains its own fractional divider and VCO, so changing one output frequency does not perturb the others. This independence is critical in systems where the application processor, memory controller, PHY, and fabric clocks must run at unrelated rates, eliminating the need for multiple oscillators and reducing board area by up to 80 percent versus discrete XO banks.
Typical applications include FPGA/ASIC reference clock generation, networking switches and routers, server and storage backplanes, broadcast video timing, industrial test and measurement, and any multi-rail system that previously required four separate crystal oscillators. The wide output format support makes it equally suitable for legacy CMOS logic and modern LVDS SerDes interfaces. As a Skyworks ClockBuilder Pro configurable device, every orderable part number such as the B03900-GMR suffix encodes a specific factory-programmed frequency plan, but the silicon itself is identical across the family.
Design consideration: the exposed pad (EP) on the QFN-24-EP package must be soldered to a sufficient ground copper pour for thermal dissipation and low-inductance ground return. Place the input reference crystal within 5 mm of the XIN/XOUT pins and follow the datasheet's four-layer reference layout for skew-critical applications.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for SI5335B-B03900-GMR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with SI5335B-B03900-GMR (same form factor and footprint) — differing in Number of Outputs, Output Frequency Range, Package, MSL Level, Configuration Interface.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SI5335B-B03897-GMR
✅ Drop-In📋 Reference alternative (not in catalog)
SI5335B-B11355-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI5335A-B-GMR
✅ Drop-In📋 Reference alternative (not in catalog)
SI5335A-B-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI5335-B-GMR
✅ Drop-In📋 Reference alternative (not in catalog)
SI5335B-B03900-GMR Specifications
| Manufacturer | Skyworks Solutions (formerly Silicon Labs) |
| Part Number Suffix | B03900-GMR (custom frequency plan) |
| Function | 4-output any-frequency clock generator |
| Number of Outputs | 4 (each configurable as 1 differential pair or 2 single-ended) |
| Output Frequency Range | 1 MHz to 200 MHz per output (350 MHz with MultiSynth) |
| Synthesis Technology | MultiSynth fractional divider, 0 ppm synthesis error |
| Input Reference | External crystal or CMOS reference (XTAL input) |
| Core Supply Voltage | 1.8 V |
| Output Voltage (per bank) | 1.8 V / 2.5 V / 3.3 V configurable |
| Output Formats | LVDS, LVPECL, HCSL, CMOS (bank configurable) |
| Package | QFN-24-EP (4x4 mm) with exposed thermal pad |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +85C (industrial) |
| MSL Level | 3 (168 hours) |
| RoHS Status | Compliant |
| Lead-Free / Halogen-Free | Yes / Yes |
| Configuration Interface | I2C / SPI + Skyworks ClockBuilder Pro |
SI5335B-B03900-GMR Pin Configuration
| Pin 1 | XIN — Crystal input / external reference input |
| Pin 2 | XOUT — Crystal output (leave NC if external CMOS reference used) |
| Pin 3 | VDD_XTAL — 1.8 V supply for crystal/reference block |
| Pin 4 | VDD_CORE — 1.8 V core supply |
| Pin 5 | VDD_BANK0 — Output bank 0 supply (1.8/2.5/3.3 V) |
| Pin 6 | OUT0A — Output bank 0, channel A (differential or single-ended) |
| Pin 7 | OUT0B — Output bank 0, channel B (differential or single-ended) |
| Pin 8 | VDD_BANK1 — Output bank 1 supply (1.8/2.5/3.3 V) |
| Pin 9 | OUT1A — Output bank 1, channel A |
| Pin 10 | OUT1B — Output bank 1, channel B |
| Pin 11 | VDD_BANK2 — Output bank 2 supply (1.8/2.5/3.3 V) |
| Pin 12 | OUT2A — Output bank 2, channel A |
| Pin 13 | OUT2B — Output bank 2, channel B |
| Pin 14 | VDD_BANK3 — Output bank 3 supply (1.8/2.5/3.3 V) |
| Pin 15 | OUT3A — Output bank 3, channel A |
| Pin 16 | OUT3B — Output bank 3, channel B |
| Pin 17 | SDA — I2C serial data (or SPI MOSI) |
| Pin 18 | SCL — I2C serial clock (or SPI SCLK) |
| Pin 19 | CSb — SPI chip select (active low) / I2C address select |
| Pin 20 | INTb — Interrupt output (active low, open-drain) |
| Pin 21 | RSTb — Reset input (active low) |
| Pin 22 | FS — Frequency select / multi-function pin |
| Pin 23 | VSS — Ground reference |
| Pin 24 | VSS — Ground reference |
Typical Applications
SI5335B-B03900-GMR is suitable for 6 applications: FPGA and ASIC Reference Clock Generation, Networking Switch and Router Timing, Server and Storage Backplane Clocking, Broadcast Video and Professional AV Timing, Industrial Test and Measurement Equipment, Medical Imaging and Diagnostic Equipment.
FPGA and ASIC Reference Clock Generation
The SI5335B-B03900-GMR's 0 ppm MultiSynth fractional-N synthesis accuracy and four independently programmable LVDS/LVPECL/HCSL outputs make it an ideal multi-rail clock source for FPGA and ASIC reference designs. Each of the four banks can drive a different voltage domain (1.8 V, 2.5 V, 3.3 V) without external level translation, replacing up to four crystal oscillators on the board. Engineers typically use one bank for the FPGA transceiver reference clock, another for the DDR memory controller, and the remaining two for ASIC fabric and PHY clocks. The exposed-pad QFN-24 keeps the footprint under 16 mm^2, critical for space-constrained FPGA modules.
Recommended
Networking Switch and Router Timing
Switch and router line cards require multiple unrelated clock frequencies - PHY reference, fabric, management controller, and SerDes reference - all derived from a single low-cost crystal. The SI5335B-B03900-GMR synthesizes these from one XTAL input with 0 ppm error and sub-200 ps output skew, eliminating four discrete XOs. Its LVDS and LVPECL output formats match the input requirements of GbE, 10GbE, and 100GbE PHYs directly. Industrial temperature grade (-40C to +85C) and 1.8 V core supply simplify integration with low-power network processors in thermally constrained chassis designs.
Recommended
Server and Storage Backplane Clocking
Server motherboards and storage controllers typically need a SAS/SATA PHY clock, a PCIe reference clock, a BMC clock, and an SoC clock - all unrelated. The SI5335B-B03900-GMR consolidates these into a single IC, saving BOM cost and PCB area while providing per-bank output enable for power management. The integrated 50 ohm output termination option simplifies routing on dense backplanes, and the I2C/SPI host interface allows the BMC to disable unused banks during low-power states. The 0 ppm synthesis accuracy ensures SAS/SATA and PCIe compliance across all temperature and voltage corners.
Recommended
Broadcast Video and Professional AV Timing
Professional video equipment needs multiple video-format clocks (27 MHz for SD/HD, 74.25 MHz for 720p/1080p, 148.5 MHz for 1080p/4K, audio word clocks) with strict jitter performance. The SI5335B-B03900-GMR delivers each frequency with low phase noise suitable for video reference distribution. Its 0 ppm synthesis accuracy eliminates drift between audio and video clocks, solving lip-sync and chroma issues common with separate XOs. The exposed-pad QFN-24 provides the thermal headroom for continuous 24/7 broadcast operation.
Recommended
Industrial Test and Measurement Equipment
Test instruments such as oscilloscopes, logic analyzers, and protocol analyzers require precisely related clock frequencies for ADC sampling, FPGA fabric, display controllers, and communication PHYs. The SI5335B-B03900-GMR's MultiSynth architecture allows arbitrary frequency relationships, critical when the ADC sample clock and FPGA fabric must run at non-integer ratios. Per-bank output enable supports hot-swapping of measurement modules, and the wide 1.8 V/2.5 V/3.3 V output format mix lets one part drive mixed-voltage ASICs and legacy logic analyzers.
Recommended
Medical Imaging and Diagnostic Equipment
Ultrasound, MRI gradient controllers, and patient monitoring systems need multiple precision clocks for the analog front-end ADC, DSP processor, display, and communications. The SI5335B-B03900-GMR provides 0 ppm accuracy on every output, ensuring the ADC sampling clock and DSP processor clock maintain the exact relationship needed for coherent beamforming in ultrasound. The industrial temperature grade and high reliability of the QFN-24 package suit the long-life-cycle requirements of medical equipment. Skyworks' long-term supply commitment supports multi-year medical product roadmaps.
Recommended
Recommended Products Summary
Engineering reference data for SI5335B-B03900-GMR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SI5335B-B03897-GMR | SI5335B-B11355-GM | SI5335A-B-GMR | SI5335A-B-GM | SI5335-B-GMR |
|---|---|---|---|---|---|---|
| Package | QFN-24-EP (4x4 mm) | QFN-24-EP (4x4 mm) - same | QFN-24-EP (4x4 mm) - same | QFN-24-EP (4x4 mm) - same | QFN-24-EP (4x4 mm) - same | QFN-24-EP (4x4 mm) - same |
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Number of Outputs | 4 banks (4 diff or 8 SE) | 4 banks (4 diff or 8 SE) - same | 4 banks (4 diff or 8 SE) - same | 4 banks (4 diff or 8 SE) - same | 4 banks (4 diff or 8 SE) - same | 4 banks (4 diff or 8 SE) - same |
| Synthesis Accuracy | 0 ppm (MultiSynth) | 0 ppm - same | 0 ppm - same | 0 ppm - same | 0 ppm - same | 0 ppm - same |
| Output Format Flexibility | LVDS/LVPECL/HCSL/CMOS per bank | LVDS/LVPECL/HCSL/CMOS per bank - same | LVDS/LVPECL/HCSL/CMOS per bank - same | Fixed per bank (CMOS or LVDS) | Fixed per bank (CMOS or LVDS) | Single format per bank (less flexible) |
| Factory Frequency Plan | B03900 (custom ClockBuilder Pro) | B03897 (different plan) | B11355 (different plan) | A-suffix plan | A-suffix plan | Non-B plan |
| Packaging Form | Tape & Reel (GMR suffix) | Tape & Reel | Tray (GM suffix) | Tape & Reel | Tray | Tape & Reel |
| Operating Temperature | -40C to +85C | -40C to +85C - same | -40C to +85C - same | -40C to +85C - same | -40C to +85C - same | -40C to +85C - same |
Key Differentiators
- 0 ppm synthesis accuracy across all four banks independently (vs SI5335 (non-B variant) and competitive 4-output PLLs)
- Per-bank configurable output format (LVDS/LVPECL/HCSL/CMOS) (vs SI5335A-B-GMR)
- Industry-leading sub-200 ps output-to-output skew in 4x4 mm package (vs Larger 4-output clock generators in QFN-32 or QFN-40 packages)
Design Notes
Estimated: the 24-pin QFN-EP package's exposed thermal pad (pin 25, not counted in pin numbers) must be soldered to a continuous ground copper pour of at least 25 mm^2 on the top side, with thermal vias (0.3 mm drill, 0.6 mm pitch, 4-6 vias) connecting to an inner ground plane. This provides low-inductance ground return and meets the datasheet's 0.7 W dissipation rating at 85C ambient. Without proper EP soldering, output jitter increases by approximately 15-25 percent.
Place the input crystal within 5 mm of the XIN/XOUT pins and surround both pins with a ground guard ring to prevent switching noise from coupling into the reference. Route the four output bank traces with matched lengths within each bank (length matching tolerance < 1 mm for sub-200 ps skew) and avoid routing output traces parallel to power traces for more than 5 mm to minimize crosstalk. Use 50 ohm controlled-impedance traces (typically 0.2 mm wide on 0.2 mm dielectric) for LVDS/LVPECL outputs.
Do not skip the decoupling capacitors - each VDD pin requires a 100 nF X7R ceramic placed within 2 mm of the pin, plus a bulk 10 uF tantalum or ceramic on the core supply. Leaving VDD_BANKx floating for unused banks still requires decoupling. When using an external CMOS reference instead of a crystal, XOUT must be left floating (no-connect) per the datasheet, not grounded, or the reference input loading will shift the output frequency by several ppm.
The Si5335B-B03900-GMR requires a 1.8 V core supply plus per-bank VDD_BANK supplies that can be 1.8 V, 2.5 V, or 3.3 V depending on output format. Power sequencing requires the core supply to rise before or simultaneously with the bank supplies; out-of-sequence power-up can latch the device in an indeterminate state requiring RSTb toggle. Estimated total supply current at full 4-bank LVDS operation: ~95 mA core + ~40 mA per bank = ~255 mA worst case; design the LDO budget accordingly.
Compliance Information
RoHS compliant per Skyworks product page and JLCPCB listing. Not AEC-Q100 qualified - this is a commercial/industrial-grade part not intended for automotive safety applications. Lead-free and halogen-free per datasheet materials declaration.
