SN65LVDT100DGK - 2Gbps LVDS Repeater/Translator | Texas Instruments
MPN: SN65LVDT100DGK ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3.12 | $3.12 |
| 10 | $2.83 | $28.30 |
| 100 | $2.45 | $245.00 |
| 500 | $2.1 | $1,050.00 |
| 1,000 | $1.85 | $1,850.00 |
SN65LVDT100DGK Overview
A differential repeater/translator is an interface IC that sits in a high-speed serial signal path, receiving a degraded or logic-incompatible differential signal and re-driving it with fresh, standard-compliant output levels. Within the signal-chain hierarchy, it belongs to the buffer/repeater family of interface ICs, bridging logic families (LVDS, LVPECL, CML) that would otherwise require discrete level-shifting networks and termination circuitry.
Key features include a maximum total jitter of 100 ps, low part-to-part skew, and receiver input threshold hysteresis of tens of millivolts for noise immunity on marginal input signals. A distinctive advantage is the integrated 110-ohm differential line termination resistor, which shortens stub length, reduces component count, and saves board space compared with discrete 100-ohm termination schemes. TI positions this device as a low-power alternative to the MC100EP16 ECL repeater.
Architecturally, the receiver front-end accepts a wide-range differential input (LVDS, PECL, or CML swings) and drives a current-mode LVDS output stage designed for 100-ohm differential transmission lines. The short signal path through the device (analog repeat, no FIFO or retiming logic) keeps propagation delay low, and TI's Bipolar/high-speed process supports multi-gigabit signaling while remaining within a modest supply-current budget at 3.3 V.
Typical applications include backplane and point-to-point LVDS link conditioning, clock distribution and repeating in telecom and networking equipment, and extending LVDS display or camera links where cable losses degrade eye diagrams. Where a PECL output is required instead of LVDS, the companion SN65LVDS100/SN65LVDT101 family members cover that case in related packages.
Design consideration: keep the input traces to the integrated termination as short as possible; the device must receive a differential signal that crosses its threshold window with hysteresis, so check eye margins at 2 Gbps with your actual channel loss before committing to layout.
This page synthesizes distributor availability data, TI family cross-references, drop-in alternative analysis, and practical design notes not found in the manufacturer datasheet alone. Pricing shown is as of 2026-10-19 and is an estimate pending live distributor verification.
Drop-in alternatives for SN65LVDT100DGK — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with SN65LVDT100DGK (same form factor and footprint) — differing in Function, Input Signal Types, Package, Part-to-Part Skew, Propagation Delay.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SN65LVDT101DGK
✅ Drop-In📋 Reference alternative (not in catalog)
SN65LVDS100DGK
✅ Drop-In✓ In Stock
$1.49 / Unit
View Datasheet →SN65CML100DGK
✅ Drop-In📋 Reference alternative (not in catalog)
SN65LVDT100DGK Specifications
| Function | LVDS/LVPECL/CML to LVDS repeater/translator |
| Number of Channels | 1 |
| Data Rate | 2 Gbps |
| Input Signal Types | LVDS, LVPECL, CML |
| Output Signal Type | LVDS |
| Supply Voltage | 3 V to 3.6 V |
| Total Jitter | 100 ps (max) |
| Propagation Delay | 470 ps |
| Integrated Line Termination | 110 ohm differential |
| Receiver Input Hysteresis | Yes (mV-scale threshold hysteresis) |
| Part-to-Part Skew | 100 ps (max) |
| Package | VSSOP-8 (DGK) |
| Mounting Type | Surface Mount |
| Packaging | Tube |
| Category | Signal Buffers, Repeaters, Splitters |
| Alternative Positioning | Low-power alternative to MC100EP16 |
SN65LVDT100DGK vssop-8 (dgk) Pin Configuration Guide
Pin configuration for SN65LVDT100DGK (vssop-8 (dgk) package). Pin numbering, functions, and connection diagrams are defined in the manufacturer datasheet. Refer to it for the exact footprint and soldering guidelines.
No detailed pinout data available for SN65LVDT100DGK.
Refer to the datasheet for full pin configuration.
Typical Applications
SN65LVDT100DGK is suitable for 6 applications: Backplane LVDS Link Conditioning, Clock Distribution and Repeating, LVDS Display and Camera Link Extension, Logic Family Translation (CML/PECL to LVDS), Test and Measurement Signal Repeat, MC100EP16 ECL Repeater Replacement.
Backplane LVDS Link Conditioning
In telecom and datacom backplanes, LVDS pairs traverse connectors and long traces that attenuate amplitude and erode the eye diagram. The SN65LVDT100DGK is placed at the connector or mid-span to regenerate the signal: its receiver accepts the degraded LVDS swing, and its output stage re-drives a clean, standard-compliant LVDS level onto the next segment at up to 2 Gbps. The integrated 110-ohm differential termination placed right at the receiver pins minimizes stub reflections compared with a discrete resistor located further away. With 100 ps maximum total jitter, the repeater leaves jitter budget for the remaining channel segments. Because it runs from a single 3.3-V rail, no negative ECL supplies are needed, simplifying backplane power design versus legacy ECL repeaters like the MC100EP16.
Recommended
Clock Distribution and Repeating
High-frequency clock trees in networking and test equipment need low skew and low added jitter. The SN65LVDT100DGK repeats LVDS, LVPECL, or CML clock signals at rates up to 2 Gbps (1 GHz clock) while adding a maximum of 100 ps total jitter and 470 ps propagation delay. Its 100 ps maximum part-to-part skew allows multiple channels clocked through separate devices to stay aligned within tight timing windows. The analog repeat path introduces no PLL-style phase re-alignment artifacts, making it transparent in the timing chain. Receiver hysteresis prevents double-triggering on slow or noisy clock edges, a common failure in marginal clock links. As TI's low-power alternative to the MC100EP16, it replaces ECL clock repeaters without negative supplies.
Recommended
LVDS Display and Camera Link Extension
LVDS display panels and industrial camera links frequently fail over cables beyond 1-2 m because differential amplitude decays below receiver thresholds. TI E2E forum threads document this exact scenario with the SN65LVDT100DGK used as an LVDS buffer for LCD panel outputs. The device is inserted at the source connector or at a mid-cable extender board: the integrated 110-ohm termination presents a controlled impedance at the repeater input, and the output re-drives a full LVDS swing into the remaining cable length. At 2 Gbps maximum rate it covers high-resolution panel data links. For very long reaches, pair it with evaluation of newer TI buffers such as DS25BR120, which the forum identifies as a modern upgrade path.
Recommended
Logic Family Translation (CML/PECL to LVDS)
Systems mixing SerDes CML outputs, PECL clock logic, and LVDS receivers need level translation without discrete resistor networks. The SN65LVDT100DGK accepts LVDS, LVPECL, or CML differential swings at its input - a wide common-mode and amplitude window - and outputs standard LVDS levels, eliminating hand-built dividers and bias networks. The integrated 110-ohm termination matches 100-ohm differential routing while accommodating the slightly different termination needs of CML sources. Because translation is analog and transparent with 470 ps propagation delay, timing analysis is straightforward: add the delay once per repeater stage. This makes the part a clean interface brick between ASIC SerDes banks and LVDS FPGA inputs at 3.3-V supply.
Recommended
Test and Measurement Signal Repeat
Instrument front ends and timing modules distribute fast differential triggers and sample clocks across boards where signal integrity degrades. The SN65LVDT100DGK provides a compact 8-pin VSSOP repeat point: 2 Gbps bandwidth, 100 ps maximum total jitter, and deterministic 470 ps delay keep trigger timing predictable across multiple channels. The receiver hysteresis tolerates the reduced slew rates typical of front-panel BNC-to-PCB transitions. Because the device is TI's low-power alternative to the MC100EP16, instrument designers can drop negative-rail ECL repeater stages and consolidate on a single 3.3-V domain, reducing supply complexity and crosstalk between power islands in dense timing modules.
Recommended
MC100EP16 ECL Repeater Replacement
Legacy designs using the ON Semiconductor/TI MC100EP16 ECL repeater can migrate to the SN65LVDT100DGK, which TI explicitly positions as a low-power alternative. The migration removes the negative ECL supply rail: the LVDT100 operates from 3 V to 3.6 V, cutting power-supply count and heat. While the footprint differs from the MC100EP16's package, the functional mapping is direct - differential in, differential out, with 100 ps-class jitter and skew. The added benefit is output-level flexibility: stay with LVDS (SN65LVDT100), move to PECL (SN65LVDS100), or CML (SN65CML100), all pin-architecture siblings in the DGK package, allowing one layout to serve multiple logic-domain variants.
Recommended
Recommended Products Summary
Engineering reference data for SN65LVDT100DGK — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SN65LVDT101DGK | SN65LVDS100DGK | SN65LVDT101D |
|---|---|---|---|---|
| Package | VSSOP-8 (DGK) | VSSOP-8 (DGK) - same | VSSOP-8 (DGK) - same | SOIC-8 (D) - different footprint |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Data Rate | 2 Gbps | 2 Gbps | 2 Gbps | 2 Gbps |
| Input Signal Types | LVDS, LVPECL, CML | LVDS, LVPECL, CML | LVDS, LVPECL, CML | LVDS, LVPECL, CML |
| Output Signal Type | LVDS | LVPECL | PECL | LVPECL |
| Integrated 110-ohm Termination | Yes | Yes | No | Yes |
| Supply Voltage | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V |
Key Differentiators
- Integrated 110-ohm differential input termination (vs SN65LVDS100DGK)
- LVDS output for direct LVDS receiver connection (vs SN65LVDT101DGK)
- Broader input family than CML-only sibling (vs SN65CML100DGK)
Design Notes
Place the SN65LVDT100DGK as close as possible to the connector or segment boundary where the degraded LVDS signal arrives. The integrated 110-ohm differential termination is effective only when input stub length is minimized; a long stub before the termination causes reflections that consume the 100 ps jitter budget. Route 100-ohm differential impedance on both sides of the device, and keep intra-pair skew under 10 ps to preserve the eye at 2 Gbps.
Decouple the 3.3-V pin with at least 0.1 uF ceramic placed within 2 mm of the supply pin, plus a bulk 1-10 uF per device. The output stage drives a full LVDS swing (~3.5 mA current-mode), so supply noise couples into output timing; a clean analog 3.3-V rail or an LC filter from a shared digital rail helps hold total jitter near the 100 ps maximum. Never share the repeater supply trace with switching-regulator loads.
Do not substitute SN65LVDS100DGK (PECL output) or SN65CML100DGK (CML output) on the same footprint without checking the downstream receiver's logic thresholds - all three share the DGK footprint but output different levels. Also verify the input differential amplitude actually crosses the receiver threshold window at your cable length; TI E2E reports of non-working 5 m LVDS links show the repeater cannot recover a signal that is already below threshold at its pins. Estimated: at 2 Gbps, a single 470 ps repeater delay is less than one bit period (500 ps), so one repeater stage typically closes timing without redesign.
Compliance Information
RoHS compliance and lead-free status per TI product family conversion; confirm exact material declarations via TI.com quality pages for the ordering MPN. REACH, halogen-free, and conflict-minerals statements were not present in the provided data.
