THS1031IPWG4 - 10-Bit 30 MSPS ADC Single Ch. | Texas Instruments
MPN: THS1031IPWG4 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.63 | $5.63 |
| 10 | $5.07 | $50.70 |
| 100 | $4.5 | $450.00 |
| 500 | $3.94 | $1,970.00 |
| 1,000 | $3.38 | $3,380.00 |
THS1031IPWG4 Overview
A pipelined ADC is a type of analog-to-digital converter that processes the analog input through a series of low-resolution stages, each producing a partial digital code that is combined in a digital correction stage. Pipelined ADCs trade slightly higher pipeline latency (typically a few clock cycles) for high conversion throughput at low per-conversion power, making them the dominant topology for video, imaging, communications, and instrumentation sample rates from a few MSPS to over 100 MSPS. The THS1031 occupies the lower-resolution, lower-cost end of this family.
Key features include configurable input functions - single-ended, single-ended with analog clamp, and single-ended with programmable digital clamp - which let the user optimize the front-end for video, CCD, or general-purpose signal acquisition. The 10-bit resolution delivers 1024 quantization levels, suitable for composite video digitization, low-cost digital still cameras, CCD signal processing, and general-purpose data acquisition at sample rates up to 30 MSPS. Integrated programmable gain lets the user scale the input full-scale range without external amplifiers.
Designers typically pair the THS1031 with a low-jitter clock source and a 50-ohm terminated analog front end to realize the full 30 MSPS throughput. A key design consideration is supply decoupling: place 0.1 uF ceramic bypass capacitors as close as possible to the AVD and DVD pins, and provide a separate analog and digital ground plane joined at a single point under the ADC to avoid digital switching noise coupling into the analog front end.
Typical applications include video digitizers, set-top box input stages, CCD signal chains, general-purpose data acquisition front ends, and industrial imaging subsystems. The TSSOP-28 package supports standard surface-mount assembly and reflow profiles compatible with lead-free (RoHS) processes, simplifying high-volume manufacturing. This page synthesizes distributor pricing, drop-in alternatives, and design notes for the THS1031IPWG4 not found in the manufacturer datasheet alone.
Drop-in alternatives for THS1031IPWG4 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with THS1031IPWG4 (same form factor and footprint) — differing in Package, Architecture, RoHS Status, Input Type, Number of Channels.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
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THS1031IDWR
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View Datasheet →THS1030IPWR
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ADS901E/250
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THS1031IPWG4 Maximum Ratings & Electrical Characteristics
| Number of Bits | 10 |
| Sampling Rate | 30 MSPS |
| Number of Inputs | 1 |
| Input Type | Single-Ended (configurable) |
| Data Interface | Parallel |
| Architecture | Pipelined |
| Supply Voltage (Analog/Digital) | 3.0 V to 5.5 V |
| Operating Temperature | -40C to +85C |
| Package / Case | 28-TSSOP (0.173 inch / 4.40 mm width) |
| Mounting Type | Surface Mount |
| Packaging | Tube |
| Input Functions | Single-ended, single-ended + analog clamp, single-ended + programmable digital clamp |
| Programmable Gain | Yes (integrated) |
| Out-of-Range Indicator | Yes |
| Power-Down Pin | Yes |
| Temperature Grade | Industrial |
| Terminal Form | Gull Wing |
| RoHS Status | Compliant (G4 suffix denotes lead-free / green) |
THS1031IPWG4 Pin Configuration
| Pin 1 | AGND — Analog ground return |
| Pin 2 | AIN — Analog input (single-ended) |
| Pin 3 | AGND — Analog ground return |
| Pin 4 | AVD — Analog supply voltage (3.0-5.5 V) |
| Pin 5 | REFBS — Reference bottom (decouple to AGND) |
| Pin 6 | REFTS — Reference top (decouple to AGND) |
| Pin 7 | REFT — Reference top output (decouple) |
| Pin 8 | REFB — Reference bottom output (decouple) |
| Pin 9 | AGND — Analog ground |
| Pin 10 | CLAMP — Analog clamp input (sync tip) |
| Pin 11 | GAIN — Programmable gain control |
| Pin 12 | PD — Power-down (active high) |
| Pin 13 | OR — Out-of-range indicator |
| Pin 14 | DGND — Digital ground |
| Pin 15 | CLK — Clock input (up to 30 MHz) |
| Pin 16 | DVD — Digital supply voltage (3.0-5.5 V) |
| Pin 17 | DGND — Digital ground |
| Pin 18 | D9 — Data output bit 9 (MSB) |
| Pin 19 | D8 — Data output bit 8 |
| Pin 20 | D7 — Data output bit 7 |
| Pin 21 | D6 — Data output bit 6 |
| Pin 22 | D5 — Data output bit 5 |
| Pin 23 | D4 — Data output bit 4 |
| Pin 24 | D3 — Data output bit 3 |
| Pin 25 | D2 — Data output bit 2 |
| Pin 26 | D1 — Data output bit 1 |
| Pin 27 | D0 — Data output bit 0 (LSB) |
| Pin 28 | NC — Not connected (per datasheet) |
Typical Applications
THS1031IPWG4 is suitable for 6 applications: Composite Video Digitizer, CCD Signal Chain Digitizer, General-Purpose Data Acquisition Front End, Set-Top Box Video Input, Industrial Imaging Subsystem, Portable / Battery-Powered Imaging.
Composite Video Digitizer
The THS1031IPWG4 is a strong fit for composite video (NTSC/PAL) digitizing front ends because its 30 MSPS sample rate exceeds the NTSC 14.3 MSPS and PAL 17.7 MSPS rates with headroom for 2x oversampling, and its 10-bit resolution (1024 quantization levels) preserves luminance/chroma fidelity for broadcast or surveillance-grade capture. The integrated programmable analog clamp restores the sync-tip DC level on AC-coupled video, eliminating external clamping transistors and reducing BOM cost. Placed after a video amplifier/filter network with 75-ohm termination, the converter delivers a parallel 10-bit CCIR-601 friendly stream that a downstream FPGA or ASIC can store, scale, or display. Unlike a higher-resolution 12-/14-bit ADC, the 10-bit pipeline keeps per-conversion power low, which matters for multi-channel set-top box or video capture card designs.
Recommended
CCD Signal Chain Digitizer
The THS1031IPWG4 suits CCD (charge-coupled device) signal chain digitizing because its single-ended input with programmable gain lets designers match the CCD output swing without a dedicated external PGA, and its 30 MSPS rate supports VGA-class area sensors running at up to 30 fps. The integrated digital clamp function eliminates the correlated double-sampling drift that plagues DC-coupled CCD front ends, simplifying the analog path. Placed between the CCD output buffer and a digital image processor, the converter provides a parallel 10-bit pixel stream at the sensor's pixel clock. Compared with a 12-bit alternative, the 10-bit pipeline keeps conversion latency and power low enough for hand-held industrial cameras and barcode scanners where thermal budget is tight.
Recommended
General-Purpose Data Acquisition Front End
The THS1031IPWG4 works well in general-purpose data acquisition (DAQ) front ends where 10-bit resolution and 30 MSPS throughput meet intermediate-frequency signal capture needs without the cost of 14-/16-bit precision ADCs. Its 3.0 V to 5.5 V supply range matches both 3.3 V DSP/FPGA-based systems and legacy 5 V analog boards, simplifying mixed-voltage designs. The integrated power-down pin enables gated acquisition modes where the converter idles between bursts, useful for battery-powered instrumentation and ultrasonic ranging. Placed on the analog input of an FPGA-based DAQ card, the converter produces a parallel 10-bit stream aligned to the system clock with minimal pipeline latency. Engineers migrating from 8-bit systems gain 4x more quantization levels at comparable cost.
Recommended
Set-Top Box Video Input
The THS1031IPWG4 is a cost-effective video input ADC for set-top box (STB) auxiliary video inputs, where composite or component video from external sources needs to be digitized at broadcast rates and routed to the main decoder. Its 30 MSPS rate exceeds component-video bandwidth (typically 13.5 MHz luma / 6.75 MHz chroma for SDTV) with substantial oversampling margin, and its small 28-TSSOP footprint saves PCB area in space-constrained STB mainboards. The integrated analog clamp and programmable gain absorb the level variations of consumer-grade A/V sources without external conditioning. Compared with broadcast-grade 12-/14-bit ADCs, the 10-bit pipeline keeps per-channel cost low enough to fit multiple-input STB designs.
Recommended
Industrial Imaging Subsystem
The THS1031IPWG4 supports industrial imaging subsystems including machine-vision line-scan cameras, bar-code readers, and inspection equipment that need 10-bit grayscale digitization at up to 30 MSPS. Its industrial -40C to +85C operating range suits factory-floor enclosures and outdoor installations, while its integrated programmable gain handles the wide dynamic range of line-scan sensors without external PGAs. The parallel output interface streams directly into an FPGA or ASIC for real-time thresholding, edge detection, or barcode decode, with no high-speed serial protocol overhead. The power-down pin enables duty-cycled operation in battery-powered portable barcode scanners, extending field runtime. Compared with CCD-specific 12-bit ADCs, this part delivers the lowest cost-per-channel for 10-bit applications.
Recommended
Portable / Battery-Powered Imaging
The THS1031IPWG4 fits portable and battery-powered imaging devices including handheld digital scopes, low-end camcorders, and wireless inspection cameras because its 3.0 V to 5.5 V supply works directly from a single Li-ion cell (3.0-4.2 V) and its dedicated power-down pin drops quiescent current between active acquisitions. The 30 MSPS sample rate supports QVGA-class CMOS sensors at 30 fps, while the TSSOP-28 footprint is small enough for handheld form factors. The integrated clamp and gain remove external analog components, shrinking the BOM and saving precious PCB real estate. Compared with full 12-/14-bit ADCs, this 10-bit pipeline keeps average conversion power well under 100 mW at 30 MSPS - critical for extending battery runtime in field instruments.
Recommended
Recommended Products Summary
Engineering reference data for THS1031IPWG4 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | THS1031IPWR | THS1031IPW | THS1031IDWR | THS1030IPWR |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 28-TSSOP (PW) | 28-TSSOP (PW) - same | 28-TSSOP (PW) - same | 28-SOIC (DW) - wider body | 28-TSSOP (PW) - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit |
| Sample Rate | 30 MSPS | 30 MSPS | 30 MSPS | 30 MSPS | 30 MSPS |
| Supply Voltage | 3.0 V to 5.5 V | 3.0 V to 5.5 V | 3.0 V to 5.5 V | 3.0 V to 5.5 V | 3.0 V to 5.5 V |
| Programmable Digital Clamp | Yes | Yes | Yes | Yes | No (THS1030 omits digital clamp) |
| Lead-Free (RoHS) | Yes (G4 green finish) | Yes (lead-free) | No (standard Pb finish) | Yes (lead-free) | Yes (lead-free) |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Key Differentiators
- Integrated programmable digital clamp eliminates external clamp circuitry (vs THS1030IPWR)
- Lead-free RoHS-compliant green finish with same TSSOP-28 footprint (vs THS1031IPW)
- Same electrical die in wider SOIC-28 body for hand-solder friendly prototyping (vs THS1031IDWR)
- Single 3.0-5.5 V supply with integrated power-down pin (vs THS1030IPWR)
Design Notes
Use a split ground plane with separate analog and digital sections, joined at a single point directly under the THS1031IPWG4 exposed paddle or AGND pin (pin 1 / pin 9). Place 0.1 uF ceramic decoupling capacitors as close as possible to AVD (pin 4) and DVD (pin 16) - keep trace length under 2 mm to minimize power-rail inductance. Reference pins REFT, REFB, REFTS, REFBS each require their own 0.1 uF + 10 uF decoupling to AGND; shared reference decoupling introduces gain error and channel-to-channel mismatch.
Drive the CLK input (pin 15) with a low-jitter clock source: SNR degradation equals 20*log10(1 / (2*pi*f_in*t_jitter)), so at 10 MHz input a 50 ps RMS jitter costs ~10 dB of SNR. Place the clock buffer within 25 mm of pin 15 and route on the digital ground side of the split plane. Series-terminate the 10-bit parallel output bus (D0-D9) with 33 ohm resistors near the ADC to damp reflections if the trace length to the FPGA/ASIC exceeds 50 mm.
Use a ferrite bead between the analog (AVD) and digital (DVD) supply pins to break high-frequency noise coupling; for example, a 600-ohm @ 100 MHz BLM18PG601SN1D followed by 10 uF + 0.1 uF local decoupling on both rails. The THS1031IPWG4 power-down pin (PD, pin 12) gates both analog and digital sections; tie PD low through a 100 kohm pull-down if unused to prevent floating-state quiescent current spikes.
Do not route digital outputs (D0-D9, OR, CLK) over the analog ground plane section - this capacitively couples digital switching edges into the analog front end and degrades SNR by 5-10 dB. Avoid series inductors on AVD/DVD rails; a ferrite bead plus local decoupling is the recommended filter. The CLAMP pin (pin 10) must be AC-coupled to the analog input through a 10 nF capacitor when used in sync-tip clamping mode; DC-coupling defeats the clamp function.
The TSSOP-28 package has a thermal resistance of approximately 90 C/W (theta_JA) when mounted on a standard JEDEC 4-layer test board with no airflow. At full 30 MSPS throughput with 3.3 V supply, the THS1031IPWG4 dissipates roughly 60 mW - well within the package rating up to 85C ambient. For enclosed industrial applications above 70C ambient, add 100 LFM airflow or a 5 mm x 5 mm copper pour beneath the exposed thermal pad to keep junction temperature below 125C.
Compliance Information
G4 suffix denotes TI's lead-free green (RoHS) finish. Not AEC-Q100 qualified; industrial temperature grade only. Halogen-free status not explicitly stated in verified web data.
