THS1230CPWG4 - 12-Bit 30 MSPS Low-Power ADC | Texas Instruments
MPN: THS1230CPWG4 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.42 | $8.42 |
| 10 | $7.58 | $75.80 |
| 100 | $6.74 | $674.00 |
| 500 | $6.05 | $3,025.00 |
| 1,000 | $5.62 | $5,620.00 |
THS1230CPWG4 Overview
What is a high-speed pipeline ADC? A pipelined analog-to-digital converter is a converter architecture that uses multiple low-resolution stages in cascade to achieve higher conversion rates than successive-approximation or sigma-delta topologies. Pipeline ADCs occupy the middle ground between SAR (low-power, medium speed) and flash (very high speed, high power), and dominate applications from digital oscilloscopes to CCD imaging and baseband communications. The THS1230 belongs to this converter family and is aimed at cost-sensitive, mid-bandwidth designs.
Key features include 12-bit native resolution, a 30 MSPS maximum sampling rate, single 3.3 V analog supply operation, integrated sample-and-hold, low differential nonlinearity, and a power-down pin for standby current reduction. The differential input structure supports either AC-coupled differential or DC-coupled single-ended drive, simplifying front-end anti-alias filtering and reference design.
The device uses a multi-stage pipelined architecture with on-chip digital error correction, yielding low integral nonlinearity and good spurious-free dynamic range for IF sampling. Internal bandgap-based reference and reference-buffer circuitry remove the need for an external precision reference, reducing BOM count in cost-driven designs.
Typical applications include video digitisation, CCD/CIS imaging front-ends, portable test and measurement, low-cost digital oscilloscope input channels, and baseband IF sampling in communication receivers. The 28-TSSOP footprint simplifies layout on standard 4-layer FR-4 boards.
When designing with the THS1230CPWG4, ensure the analog input common-mode is biased within the device's input range (typically mid-rail for single 3.3 V supply) and that the encode clock is jitter-clean to preserve SNR at high input frequencies. Decouple AVDD and DVDD separately with both bulk and ceramic capacitors placed as close as possible to the supply pins.
This page synthesises distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for THS1230CPWG4 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with THS1230CPWG4 (same form factor and footprint) — differing in Architecture, Input Type, Operating Temperature, Resolution.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
THS1230IPW
✅ Drop-In📋 Reference alternative (not in catalog)
THS1230CPW
✅ Drop-In📋 Reference alternative (not in catalog)
THS1230IDW
✅ Drop-In📋 Reference alternative (not in catalog)
THS1230IDWG4
✅ Drop-In📋 Reference alternative (not in catalog)
THS1230CDWR
✅ Drop-In✓ In Stock
$5.2 / Unit
View Datasheet →THS1230CPWG4 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bit |
| Sampling Rate | 30 MSPS |
| Number of Channels | 1 |
| Input Type | Differential / Single-Ended |
| Data Interface | Parallel |
| Architecture | Pipelined |
| Supply Voltage (Analog) | 3.3 V nominal |
| Supply Voltage (Digital) | 3.3 V nominal |
| Package / Case | 28-TSSOP (0.173 in / 4.40 mm width) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +70C |
| Packaging | Tube |
| Power Down Mode | Yes (dedicated PD pin) |
| Temperature Grade | Commercial |
| Conversion Time | 0.033 us (typical at 30 MSPS) |
THS1230CPWG4 Pin Configuration
| Pin 1 | AVDD — Analog supply voltage (3.3 V nominal) |
| Pin 2 | AVSS — Analog ground |
| Pin 3 | IN+ — Differential analog input (positive) |
| Pin 4 | IN- — Differential analog input (negative) |
| Pin 5 | CM — Common-mode voltage bypass |
| Pin 6 | REFT — Top reference decoupling |
| Pin 7 | REFB — Bottom reference decoupling |
| Pin 8 | REFOUT — Internal reference output |
| Pin 9 | AVSS — Analog ground |
| Pin 10 | AVDD — Analog supply voltage |
| Pin 11 | PD — Power-down input (active high) |
| Pin 12 | CLK — Encode clock input |
| Pin 13 | DVDD — Digital supply voltage |
| Pin 14 | DVSS — Digital ground |
| Pin 15 | D11 — Data output bit 11 (MSB) |
| Pin 16 | D10 — Data output bit 10 |
| Pin 17 | D9 — Data output bit 9 |
| Pin 18 | D8 — Data output bit 8 |
| Pin 19 | D7 — Data output bit 7 |
| Pin 20 | D6 — Data output bit 6 |
| Pin 21 | D5 — Data output bit 5 |
| Pin 22 | D4 — Data output bit 4 |
| Pin 23 | D3 — Data output bit 3 |
| Pin 24 | D2 — Data output bit 2 |
| Pin 25 | D1 — Data output bit 1 |
| Pin 26 | D0 — Data output bit 0 (LSB) |
| Pin 27 | OTR — Out-of-range indicator output |
| Pin 28 | DVSS — Digital ground |
Typical Applications
THS1230CPWG4 is suitable for 6 applications: Video Digitisation and Imaging, CCD/CIS Sensor Front-End, Low-Cost Digital Oscilloscope Input, Baseband IF Sampling, Portable Test and Measurement, Industrial Data Acquisition Module.
Video Digitisation and Imaging
The THS1230CPWG4 fits video digitisation front-ends because its 30 MSPS sampling rate covers standard-definition video bandwidth (~27 MHz for BT.656) with margin, while 12-bit resolution provides 4096 grey levels for broadcast-grade imagery. Its single 3.3 V supply, differential input, and parallel CMOS output simplify interface to FPGA-based video processors such as the Spartan-6 or Cyclone IV. The differential input pair maximises even-order harmonic rejection, and the on-chip reference removes the need for an external precision reference. Placed between a THS4031 driver amplifier and the FPGA digital input pins with separate AVDD/DVDD decoupling, it adds minimal board area. Compared with the ADS4122 successor, it offers slightly higher power but equivalent functional performance in legacy designs.
Recommended
CCD/CIS Sensor Front-End
The THS1230CPWG4 suits CCD and CMOS image sensor front-ends because its 12-bit resolution captures the dynamic range of typical CIS pixel arrays, and its 30 MSPS rate supports line-scan cameras and machine-vision applications. The differential input structure rejects common-mode noise from switching sensor clock lines, while the integrated sample-and-hold preserves image fidelity across pixel boundaries. The single 3.3 V supply matches CIS analog rails, eliminating additional LDO stages. Pair it with a sensor such as the KAI-0340 or MT9V032 and an FPGA-based image pipeline; the parallel output bus feeds directly into the FPGA pixel-clock domain.
Recommended
Low-Cost Digital Oscilloscope Input
The THS1230CPWG4 fits low-cost digital oscilloscope input channels because its 30 MSPS sampling rate delivers 30 megasamples per second of bandwidth-limited waveform capture at 12-bit vertical resolution. Combined with a THS4631 high-speed input buffer and a Xilinx Spartan-6 FPGA for triggering and display rendering, it forms a compact 1-channel digitiser block. The integrated power-down pin enables channel gating for power saving when multiple input channels are multiplexed. Compared with modern 8-bit oscilloscope ADCs, the 12-bit resolution provides 16x more dynamic range for measuring low-amplitude signal details.
Recommended
Baseband IF Sampling
The THS1230CPWG4 suits baseband IF sampling in low-cost communication receivers because its 30 MSPS rate supports intermediate-frequency digitisation up to ~15 MHz under Nyquist, and its differential input maximises even-order harmonic rejection for direct-conversion architectures. The 12-bit resolution captures multi-carrier signal envelopes with sufficient margin for demodulation. Place the ADC between an IF SAW filter and an FPGA-based digital downconverter; its single 3.3 V supply simplifies power-tree design in battery-operated radio modules such as software-defined radios.
Recommended
Portable Test and Measurement
The THS1230CPWG4 fits portable test and measurement instruments because its low power consumption and single 3.3 V supply enable battery-powered designs, while 30 MSPS provides sufficient bandwidth for audio-band, ultrasonic, and low-frequency vibration analysis. The integrated power-down pin allows shutdown between acquisition bursts, extending battery life in field-portable data loggers. Pair with a low-power MCU such as the MSP430F5528 for trigger and storage control, and a low-jitter MEMS oscillator such as the SiT8103 for the encode clock.
Recommended
Industrial Data Acquisition Module
The THS1230CPWG4 suits multi-channel industrial data acquisition modules because its parallel output bus simplifies fanout to FPGAs that aggregate multiple ADC channels, and its 12-bit/30 MSPS performance handles vibration, sonar, and acoustic emission monitoring. The differential input structure rejects motor and switching-noise common-mode voltages typical in factory environments, while the 0C to +70C commercial temperature range covers most indoor cabinet installations. For outdoor or -40C plants, use the pin-compatible THS1230IPW instead. Pair with an industrial MCU such as the TMS320F28335 for motor-control signal sampling.
Recommended
Recommended Products Summary
Engineering reference data for THS1230CPWG4 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | THS1230IPW | THS1230CPW | THS1230IDW | THS1230IDWG4 | THS1230CDWR |
|---|---|---|---|---|---|---|
| Package | 28-TSSOP (PW) | 28-TSSOP (PW) - same | 28-TSSOP (PW) - same | 28-SOIC (DW) - same body width | 28-SOIC (DW) - same body width | 28-SOIC (DW) - same body width |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Sampling Rate | 30 MSPS | 30 MSPS | 30 MSPS | 30 MSPS | 30 MSPS | 30 MSPS |
| Operating Temperature | 0C to +70C (Commercial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Data Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS |
| Lifecycle Status | Obsolete | Obsolete (last-time-buy stock) | Obsolete (last-time-buy stock) | Obsolete (last-time-buy stock) | Obsolete (last-time-buy stock) | Obsolete (last-time-buy stock) |
Key Differentiators
- Industrial temperature grade option in same package (vs THS1230CPW)
- Pin-compatible with wide-body SOIC package (vs THS1230IDW)
- On-chip reference and sample-and-hold (vs Discrete ADC + external reference)
Design Notes
Decouple AVDD with 10 uF bulk + 0.1 uF ceramic placed within 5 mm of pins 1, 10; decouple DVDD with 1 uF + 0.1 uF near pins 13, 14, 28. Per TI THS1230 datasheet recommendation, separate analog and digital ground planes should join only at the AVSS/DVSS pins of the device (single-point star ground) to prevent digital switching noise from coupling into the analog front end via ground bounce.
Route the encode clock (pin 12) on a controlled-impedance trace with series damping resistor (33 ohm) close to the pin to suppress overshoot. Keep parallel output data bus traces matched within 5 mm of each other and length-matched to within 1 cm to minimise channel-to-channel skew. Place the device away from switching power inductors; if a switching regulator is used upstream, add a ferrite bead and LC pi-filter on the analog supply rail.
Estimated: at 30 MSPS encode clock with 50 ohm source impedance, expect approximately 1.0 ns rise time at the CLK pin; total aperture jitter of the THS1230 sample-and-hold is typically 0.5 ps rms per the family datasheet, which preserves SNR up to ~10 MHz analog input. For higher IF frequencies, consider the ADS4122 successor or apply a low-jitter clock source such as the SiT9102 to maintain ENOB. Use the OTR pin (pin 27) to detect input over-range and adjust the front-end gain accordingly.
Do not leave the PD pin (pin 11) floating - tie it to DVSS through a 100 kohm pull-down to guarantee normal operation at power-up. Do not apply analog input voltages beyond AVDD+0.3 V or below AVSS-0.3 V; the input ESD diodes will forward-conduct and distort the conversion. The internal reference (REFOUT, pin 8) should be bypassed with 0.1 uF to AVSS - omitting this capacitor increases reference noise and degrades SNR by approximately 3 dB.
Compliance Information
RoHS and REACH compliance status not stated in Verified Web Data snippet for THS1230CPWG4 - marked unknown per data authenticity rules. The G4 suffix typically indicates a lead-free green-packing variant per TI convention, but explicit compliance data was not provided. AEC-Q100 not qualified (commercial-grade part); choose the THS1230IPW for industrial deployments.
